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| TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF26AXBG Semiconductor Company TMP92CF26A CMOS 32-Bit Microcontroller TMP92CF26AXBG 1. Outline and Features The TMP92CF26A is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CF26AXBG is housed in a 228-pin BGA package. (1) CPU: 32-bit CPU (High-speed 900/H1 CPU) * * * * Compatible with TLCS-900/L1 instruction code 16 Mbytes of linear address space General-purpose register and register banks Micro DMA: 8channels (62.5 ns/4 bytes at fSYS = 80 MHz, best case) (2) Minimum instruction execution time: 12.5 ns (at fSYS = 80 MHz) (3) Internal RAM: 144 Kbytes (can be used for program, data and display memory) Internal ROM: 8 Kbytes (memory for Boot only) Possible downloading of user program through either USB, UART. RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 20070701-EN * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 92CF26A-1 2007-11-21 TMP92CF26A (4) External memory expansion * * * * * Expandable up to 3.1 Gbytes (shared program/data area) Can simultaneously support 8-and 16-bit width external data buses ...... Dynamic data bus sizing Separate bus system Chip select output: 4 channels One channel in 4 channels is enabled detailed AC enable setting (5) Memory controller (6) 8-bit timers: 8 channels (7) 16-bit timer/event counter: 2 channels (8) General-purpose serial interface: 1 channel * * UART/synchronous mode IrDA ver.1.0 (115.2 kbps) selectable (There is the restriction in the setting baud rate when use this function together other functions) (9) Serial bus interface: 1 channel * * * * I2C bus mode only Supports USB (ver.1.1) Full-speed (12 Mbps) (Low-speed is not supported.) Endpoint 0: Control 64 bytes x 1 FIFO Endpoint 1: BULK (output) 64 bytes x 2 FIFOs Endpoint 2: BULK (input) 64 bytes x 2 FIFOs Endpoint 3: Interrupt (input) 8 bytes x 1 FIFO * * * * * * * * * * * Descriptor RAM: 384 bytes I2S bus mode selectable (Master, transmission only) Data Format is supported Left/Right Justify 128-byte FIFO buffer (64 bytes x 2) per channel Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN Supports 4096/65536/262144/16777216 colors for TFT Supports PIP (Picture In Picture Display) Supports H/W Rotation function for support to various LCDM Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate) SDRAM Possible to execute instruction on SDRAM Based on TC8521A (11) I2S (Inter-IC Sound)interface: 2 channels (10) USB (universal serial bus) controller: 1 channel (12) LCD controller (13) SDRAM controller: 1 channel (14) Timer for real-time clock (RTC) 92CF26A-2 2007-11-21 TMP92CF26A (15) Key-on wakeup (Interrupt key input) (16) 10-bit A/D converter (Built in Sample Hold circuit): 6 channels (17) Touch screen interface * Built-in Switch of Low-resistor, and available to reduce external components for shift change row/column (18) Watchdog timer (19) Melody/alarm generator * * * * * Melody: Output of a clock 4 to 5461-Hz clock Alarm: Output of 8 kinds of alarm pattern 5 kinds of interval interrupt Expandable up to 3.1 Gbytes (3 local area/8 bank method) Independent bank for each program, read data, write data, source and destination of DMAC (Odd channel/Even channel) and LCD display data 9 CPU interrupts: Software interrupt instruction and illegal instruction 38 internal interrupts: Seven selectable priority levels 9 external interrupts: Seven selectable priority levels (8-edge selectable) High-speed data transfer enable by controlling which convert micro DMA function and this function (20) MMU (21) Interrupts: 56 interrupts * * * * (22) DMAC function: 6 channels (23) Input/Output ports: 136 pins (Except Data bus (16-bit), Address bus (24-bit) and RD pin) (24) NAND Flash interface: 2 channels * * * * Direct NAND flash connection capability Supports SLC type and MLC type Supports Data Bus 8/16 bits, Page Size 512/2048 bytes Built-in Reed Solomon calculation circuits which enabled correct 4-address, and detect error more than 5-address Supports SPI mode of SD card and MMC card Built-in FIFO buffer of 32 bytes to each Input/Output Supports calculation 32 x 32 + 64 = 64 bits, 64 - 32 x 32 = 64 bits and 32 x 32 - 64 =64 bits I/O method Supports Signed calculations (25) SPI controller: 1 channel * * * * * (26) Product/Sum calculation: 1 channel 92CF26A-3 2007-11-21 TMP92CF26A (27) Standby function * * * * * * * * * Three Halt modes: IDLE2 (programmable), IDLE1, STOP Each pin status programmable for standby mode Built-in power supply management circuits (PMC) for leakage current provision Two blocks of clock doubler (PLL) supplies 48 MHz for USB and 80 MHz for CPU from 10 MHz Clock gear function: Selectable high-frequency clock fc to fc/16 Clock for Timer (fs = 32.768 kHz) Internal VCC= 1.5 V, External I/O Vcc = 3.0 to 3.6 V 2 power supplies (Internal power supply (1.4 to 1.6 V), External power supply (3.0 to 3.6 V) 228-pin FBGA: P-FBGA228-1515-0.80A5 (28) Clock controller (29) Operating voltage: (30) Package 92CF26A-4 2007-11-21 TMP92CF26A (AN0 to AN1)PG0 to PG1 (AN2, MX)PG2 (AN3, MY, ADTRG )PG3 (AN4 to AN5)PG4 to PG5 AVCC, AVSS VREFH, VREFL (PX, INT4) P96 10-bit 6ch AD Converter XWA Touch Screen I/F (TSI) 900/H1 CPU PLL H-OSC Clock gear L-OSC DVCC3A [12] DVCC3B [1] DVCC1A [5] DVCC1B [1] DVSSCOM W B D H IX IY IZ SP 32bit SR PC A C E L XBC XDE XHL XIX XIY XIZ XSP DVCC1C [1] DVSS1C [1] X1 X2 XT1 XT2 RESET DBGE (PY) P97 (TXD0) P90 (RXD0) P91 (CTS0, SCLK0) P92 SERIAL I/O SIO0 I2S (I S0) 2 (I2S0CKO) PF0 (I2S0DO) PF1 (I2S0WS) PF2 (I2S1CKO) PF3 (I2S1DO) PF4 (I2S1WS) PF5 (SDA) PV6 (SCL) PV7 D+ D(X1USB) PX5 (TA0IN, INT1) PC1 (TA1OUT, MLDALM) PM1 AM [1:0] PZ0 (EI_PODDATA) PZ1 (EI_SYNCLK) PZ2 (EI_PODREQ) PZ3 (EI_REFCLK) PZ4 (EI_TRGIN) PZ5 (EI_COMRESET) PZ6 (EO_MCUDATA) PZ7 (EO_MCUREQ) PM7 (PWE) PC0 (INT0) PC2 (INT2) D0 to D7 P10 to P17 (D8 to D15) IS (I2S1) SBI (I Cbus) USB Controller 8BIT TIMER (TMRA0) 8BIT TIMER (TMRA1) 8BIT TIMER (TMRA2) 8BIT TIMER (TMRA3) 8BIT TIMER (TMRA4) 8BIT TIMER (TMRA5) 8BIT TIMER (TMRA6) 8BIT TIMER (TMRA7) 16BIT TIMER (TMRB0) 16BIT TIMER (TMRB1) 2 2 DSU F PMC WATCH-DOG TIMER MMU MAC DMAC Interrupt Controller PORT1 PORT4 PORT5 PORT6 PORT7 (TA2IN, INT3) PC3 (TA3OUT) PP1 P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 ( RD ) P73 (EA24) P74 (EA25) P75 (R/ W , NDR/ B ) P76 ( WAIT ) P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 , CSXA ) P84 ( CSZB ) P85 ( CSZC ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P86 ( CSZD , ND0CE ) P87 ( CSXB , ND1CE ) PJ5 (NDALE) PJ6 (NDCLE) PA0 to PA7 (KI0 to KI7) PN0 to PN7 (KO0 to KO7) PC7 (KO8) (TA5OUT) PP2 (TA7OUT, INT5) PP3 (TB0IN0, INT6) PP4 (TB0OUT0) PP6 (TB1IN0, INT7) PP5 (TB1OUT0) PP7 (SPDI) PR0 (SPDO) PR1 ( SPCS ) PR2 (SPCLK) PR3 (LCP0) PK0 (LLOAD) PK1 (LFR) PK2 (LVSYNC) PK3 (LHSYNC) PK4 (LGOE2 to 0) PK7 to 5 (LD7 to 0) PL7 to 0 (LD15 to 8) PT7 to 0 (LD22 to 16) PU6 to 0 (LD23, EO_TRGOUT) PU7 PORT8 SPI Controller 144KB RAM NAND-FLASH I/F (2ch) LCD Controller BOOT ROM 8KB KEY-BOARD I/F RTC MELODY/ ALARM-OUT PM2 ( ALARM , MLDALM ) (CLKOUT, LDIV) PX4 PX7 ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (SDCKE) PJ7 (SDCLK) PF7 PORTV SDRAM Controller PV3 PV4 PV0 (SCLK0) PV1 PV2 PW7 to PW0 PC4 (EA26) PC5 (EA27) PC6 (EA28) Figure 1.1 Block Diagram of TMP92CF26A 92CF26A-5 2007-11-21 TMP92CF26A 2. Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CF26A, their names and functions are as follows; 2.1 Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CF26A. A1 B1 C1 D1 E1 F1 A2 B2 C2 D2 E2 F2 A3 B3 C3 D3 E3 F3 E4 F4 F6 F7 F8 F9 F10 F11 G12 H12 A4 B4 C4 A5 B5 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 B8 C8 D8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B9 B10 B11 B12 B13 B14 B15 B16 B17 C9 C10 C11 C12 C13 C14 C15 C16 C17 D9 D10 D11 D12 D13 D15 D16 D17 E14 E15 E16 E17 F14 F15 F16 F17 G14 G15 G16 G17 H14 H15 H16 H17 J14 J15 J16 J17 K14 K15 K16 K17 L14 L15 L16 L17 M14 M15 M16 M17 N14 N15 N16 N17 P5 R4 T4 U4 R5 T5 U5 P6 R6 T6 U6 P7 R7 T7 U7 P8 R8 T8 U8 P9 P10 P11 P12 P13 P15 P16 P17 G1 G2 G3 G4 H1 J1 K1 L1 H2 J2 K2 L2 H3 J3 K3 L3 H4 J4 K4 L4 G6 G7 H6 J6 K6 L6 TMP92CF26A P-FBGA228 J12 K12 L12 TOP VIEW M1 M2 M3 M4 N1 P1 R1 T1 U1 N2 P2 R2 T2 U2 N3 P3 R3 T3 U3 N4 M6 M7 M8 M9 M10 M11 M12 R9 R10 R11 R12 R13 R14 R15 R16 R17 T9 T10 T11 T12 T13 T14 T15 T16 T17 U9 U10 U11 U12 U13 U14 U15 U16 U17 Figure 2.1.1 Pin assignment diagram (P-FBGA228) 4 balls of A1, A17, U1 and U17 (most outside 4 corner of BGA package) are Dummy Balls. These balls are not connected with internal LSI chip, electrical characteristics. A1 and U1, A17 and U17 are shorted in internal package. It is recommended that using to OPEN check of mounting if mounting this LSI to Target board. Example: If checking signal (or voltage) via A1-U1-U17-A17, short U17 and U1 on Target board beforehand, and input signal (or voltage) from A1, and check voltage of A17. 92CF26A-6 2007-11-21 TMP92CF26A Table 2.1.1 Pin number and the name Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D5 D6 D7 D8 Pin name Dummy1 PG2,AN2, MX PA6,KI6 PA5,KI5 PA3,KI3 PA1,KI1 DVCC1A5 PF1,I2S0DO PJ6,NDCLE PJ1, SDCAS , SRLUB P87, CSXB , ND1CE P83, CS3 , CSXA P81, CS1 , SDCS P72, WRLU , NDWE P70, RD P65,A21 Dummy3 VREFH PG5,AN5 PG3,AN3,MY, ADTRG PA7,KI7 PA2,KI2 PA0,KI0 PF2,I2S0WS PF0,I2S0CKO PJ5,NDALE PJ2, SDWE , SRWR PJ0, SDRAS , SRLLB P86. CSZD , ND0CE P82, CS2 , CSZA , SDCS P75,R/ W ,NDR/ B P71, WRLL , NDRE P64,A20 DVCC1A4 AVCC VREFL PG4,AN4 PG1,AN1 PA4,KI4 PC5,EA27 P76, WAIT PF5,I2S1WS PF3,I2S1CKO PJ7,SDCKE PJ3,SDLLDQM P84, CSZB P80, CS0 P67,A23 P66,A22 P63,A19 P62,A18 P97,PY AVSS PW0 PG0,AN0 PC6,EA28 PC4,EA26 P74,EA25 Ball No. D9 D10 D11 D12 D13 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F6 F7 F8 F9 F10 F11 F14 F15 F16 F17 G1 G2 G3 G4 G6 G7 G12 G14 G15 G16 G17 H1 H2 H3 H4 H6 H12 H14 H15 H16 H17 J1 J2 J3 J4 J6 J12 J14 Pin name P73,EA24 PF4,I2S1DO PF7,SDCLK PJ4,SDLUDQM P85, CSZC PU6,LD22 P61,A17 P60,A16 P96,PX,INT4 PW1 PW2 PW3 PU7,LD23,EO_TRGOUT PU4,LD20 P57,A15 P56,A14 DVCC1B1 PW6 PW5 PW4 DVCC3A12 DVCC3A11 DVSS11 DVCC3A10 DVSS10 DVCC3A9 PU5,LD21 PU2,LD18 P55,A13 P54,A12 DVCC3B1 PW7 PV0,SCLK0 PV1 DVSS1 DVSS12 DVSS9 PU3,LD19 PU0,LD16 P53,A11 P52,A10 PV7,SCL PV6,SDA PV3 PV2 DVCC3A1 DVCC3A8 PU1,LD17 PT7,LD15 P51,A9 P50,A8 PN2,KO2 PN1,KO1 PN0,KO0 PV4 DVSS2 DVSS8 PT6,LD14 Ball No. J15 J16 J17 K1 K2 K3 K4 K6 K12 K14 K15 K16 K17 L1 L2 L3 L4 L6 L12 L14 L15 L16 L17 M1 M2 M3 M4 M6 M7 M8 M9 M10 M11 M12 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P5 P6 P7 P8 P9 P10 P11 P12 P13 P47,A7 P46,A6 Pin name PT5,LD13 Ball No. P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Pin name PK4,LHSYNC P13,D11 P14,D12 X2 PC7,KO8 PC3,INT3,TA2IN PX5,X1USB PP7,TB1OUT0 PP1,TA3OUT PP3,INT5,TA7OUT PP5,INT7,TB1IN0 PR2, SPCS PX7 PZ0,EI_PODDATA PZ2,EI_PODREQ PZ4,EI_TRGIN PZ6,EO_MCUDATA PZ7,EO_MCUREQ P15,D13 DVCC1A3 X1 AM0 AM1 PP6,TB0OUT0 PL0,LD0 PL2,LD2 PL4,LD4 PL5,LD5 PR1,SPDO PL6,LD6 PK1,LLOAD D0 D2 D4 D6 P11,D9 P12,D10 Dummy2 RESET D+ DDVCC1A2 PL1,LD1 PL3,LD3 XT1 XT2 PL7.LD7 PK0,LCP0 D1 D3 D5 D7 P10,D8 Dummy4 PN3,KO3 PN4,KO4 PN5,KO5 PN6,KO6 DVCC3A2 DVCC3A7 PT4,LD12 PT3,LD11 P45,A5 P44,A4 PK2,LFR PN7,KO7 PM1,MLDALM,TA1OUT PM7,PWE DVSS3 DVSS7 PT2,LD10 PT1,LD9 P43,A3 P42,A2 PK3,LVSYNC PC0,INT0 PM2, ALARM , MLDALM P90,TXD0 DVCC3A3 DVSS4 DVCC3A4 DVSS5 DVCC3A5 DVSS6 DVCC3A6 PK7,LGOE2 PT0,LD8 P41,A1 P40,A0 DVCC1A1 PC1,INT1,TA0IN P91,RXD0 DVSS1C PK6,LGOE1 PK5,LGOE0 P17,D15 P16,D14 DVCC1C PC2,INT2 P92,SCLK0, CTS0 PX4,CLKOUT, LDIV PP2,TA5OUT PP4,INT6,TB0IN0 PR0,SPDI PR3,SPCLK DBGE PZ1,EI_SYNCLK PZ3,EI_REFCLK PZ5,EI_COMRESET Note1: The P96, P97 and PG0~PG5 operate with the AVCC power supply. Note2: The PW0~PW7 and PV0~PV7 operate with the DVCC3B power supply. Note3: The X1 and X2 operate with the DVCC1C power supply. 92CF26A-7 2007-11-21 TMP92CF26A 2.2 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Pin name D0 to D7 P10 to P17 D8 to D15 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 RD Number of Pins 8 8 8 8 8 1 1 I/O I/O I/O I/O Output Output Output Output I/O Output Output Output I/O Output Output Data: Data bus D0 to D7 Functions Port 1: I/O port input or output specifiable in units of bits Data: Data bus D8 to D15 Port 4: Output port Address: Address bus A0 to A7 Port 5: Output port Address: Address bus A8 to A15 Port 6: I/O port input or output specifiable in units of bits Address: Address bus A16 to A23 Port 70: Output port Read: Outputs strobe signal to read external memory Port 71: Output port Write: Outputs strobe signal for writing data on pins D0 to D7 NAND Flash read: Outputs strobe signal to read external NAND-Flash Port 72: I/O port Write: Outputs strobe signal for writing data on pins D8 to D15 NAND Flash write: Write enable for NAND Flash Port 73: I/O port Expanded address 24 Port 74: I/O port Expanded address 25 Port 75: I/O port Read/Write: "High" represents read or dummy cycle; "Low" represents write cycle NAND Flash Ready(1) / Busy(0) input Port 76: I/O port Wait: Signal used to request CPU bus wait Port 80: Output port Chip select 0: Outputs "Low" when address is within specified address area Port 81: Output port Chip select 1: Outputs "Low" when address is within specified address area Chip select for SDRAM: Outputs "Low" when the address is within SDRAM address area Port 82: Output port Chip select 2: Outputs "Low" when address is within specified address area Expanded address ZA: Outputs "Low" when address is within specified address area Chip select for SDRAM: Outputs "Low" when the address is within SDRAM address area Port 83: Output port Chip select 3: Outputs "Low" when address is within specified address area Expanded address XA: Outputs "Low" when address is within specified address area Port 84: Output port Expanded address ZB: Outputs "Low" when address is within specified address area Port 85: Output port Expanded address ZC: Outputs "Low" when address is within specified address area P71 WRLL NDRE P72 WRLU NDWE 1 I/O Output Output P73 EA24 P74 EA25 P75 R/ W NDR/ B P76 WAIT 1 1 1 I/O Output I/O Output I/O Output Input I/O Input Output Output Output Output Output 1 1 1 P80 CS0 P81 CS1 SDCS P82 CS2 CSZA SDCS 1 Output Output Output Output P83 CS3 CSXA 1 Output Output Output P84 CSZB 1 1 Output Output Output Output P85 CSZC 92CF26A-8 2007-11-21 TMP92CF26A Table 2.2.1 Pin names and functions (2/6) Pin name P86 CSZD ND0CE Number of Pins 1 I/O Output Output Output Output Port 86: Output port Functions Expanded address ZD: Outputs "Low" when address is within specified address area Chip select for NAND Flash 0: Outputs "Low" when NAND Flash 0 is enable Port 87: Output port Expanded address XB: Outputs "Low" when address is within specified address area Chip select for NAND Flash 1: Outputs "Low" when NAND Flash 1 is enable Port 90: I/O port Transmit data for serial 0: programmable Open-drain output Port 91: I/O port (Schmitt-input) Receive data for serial 0 Port 92: I/O port (Schmitt-input) Clock I/O for serial 0 Enable to send data for serial 0 (Clear to send) Port 96: Input port (schmitt-input, with pull-up resistor) Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge X-Plus: Pin connected to X+ pin for Touch Screen I/F Port 97: Input port (schmitt input) Y-Plus: Pin connected to Y+ pin for Touch Screen I/F Port A0 to A7: Input port Key input 0 to 7: Pin used for key on wake-up 0 to 7 (Schmitt-input, with pull-up resistor) Port C0: I/O port (Schmitt-input) Interrupt request pin 0: Interrupt request pin with programmable rising/falling edge Port C1: I/O port (Schmitt-input) Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge Timer A0 input: Input pin for 8 bit timer 0 Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge Timer A2 input: Input pin for 8 bit timer 2 Port C4: I/O port Expanded address 26 Port C5: I/O port Expanded address 27 Port C6: I/O port Expanded address 28 Port C7: I/O port Key output 8: Key scan strobe pin (programmable Open-drain output) P87 CSXB ND1CE 1 Output Output I/O Output I/O Input I/O I/O Input Input Input Output P90 TXD0 P91 RXD0 P92 SCLK0 CTS 0 1 1 1 1 P96 INT4 PX P97 PY PA0 to PA7 KI0 to KI7 PC0 INT0 PC1 INT1 TA0IN PC2 INT2 PC3 INT3 TA2IN PC4 EA26 PC5 EA27 PC6 EA28 PC7 KO8 1 Input Output Input Input I/O Input I/O Input Input I/O Input I/O Input Input I/O Output I/O Output I/O Output I/O Output 8 1 1 1 1 1 1 1 1 92CF26A-9 2007-11-21 TMP92CF26A Table 2.2.1 Pin names and functions (3/6) Pin name PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS PF3 I2S0WS PF4 I2S1CKO PF5 I2S1WS PF7 SDCLK PG0 to PG1 AN0 to AN1 PG2 AN2 MX PG3 AN3 MY ADTRG Number of Pins 1 1 1 1 1 1 1 2 I/O I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output Output Output Input Input Input Input Output Input Input Output Input Input Input Output Output Output Output Port F0: I/O port Outputs clock for I2S0 Port F1: I/O port Outputs data for I2S0 Port F2: I/O port Outputs word select signal for I2S0 Port F3: I/O port Outputs clock for I2S1 Port F4: I/O port Outputs data for I2S1 Port F5: I/O port Outputs word select signal for I2S1 Port F7: Output port Clock for SDRAM Port G0 to G1: Input port Functions Analog input pin 0 to 1: Input pin for AD converter Port G2: Input port Analog input pin 2: Input pin for AD converter X-Minus: Pin connected to X- pin for Touch Screen I/F Port G3: Input port Analog input pin 3: Input pin for A/D converter Y-Minus: Pin connected to Y- pin for Touch Screen I/F A/D Trigger: Request signal for A/D start Port G4 to G5: Input port Analog input pin 4 to 5: Input pin for A/D converter Port J0: Output port Outputs strobe signal for SDRAM row address Data enable signal for D0 to D7 for SRAM Port J1: Output port Outputs strobe signal for SDRAM column address Data enable signal for D8 to D15 for SRAM Port J2: Output port Outputs write enable signal for SDRAM Write enable for SRAM: Outputs strobe signal to write data Port J3: Output port Data enable signal for D0 to D7 for SDRAM Port J4: Output port Data enable signal for D8 to D15 for SDRAM Port J5: I/O port Address latch enable signal for NAND Flash Port J6: I/O port Command latch enable signal for NAND Flash Port J7: Output port Clock enable signal for SDRAM 1 1 PG4 to PG5 AN4 to AN5 PJ0 SDRAS SRLLB 2 1 PJ1 SDCAS SRLUB 1 Output Output Output PJ2 SDWE SRWR 1 Output Output Output Output Output Output I/O Output I/O Output Output Output PJ3 SDLLDQM PJ4 SDLUDQM PJ5 NDALE PJ6 NDCLE PJ7 SDCKE 1 1 1 1 1 92CF26A-10 2007-11-21 TMP92CF26A Table 2.2.1 Pin names and functions (4/6) Pin name PK0 LCP0 PK1 LLOAD PK2 LFR PK3 LVSYNC PK4 LHSYNC PK5 LGOE0 PK6 LGOE1 PK7 LGOE2 PL0 to PL7 LD0 to LD7 PM1 TA1OUT MLDALM PM2 ALARM MLDALM Number of Pins 1 1 1 1 1 1 1 1 8 I/O Output Output Output Output Output Output Output Output Output Input Output Output Output Output Output Output Output Output Output Output Output Output Port K0: Output port Signal for LCD driver Port K1: Output port Signal for LCD driver: Data load signal Port K2: Output port Signal for LCD driver Port K3: Output port Functions Signal for LCD driver: Vertical sync signal Port K4: Output port Signal for LCD driver: Horizontal sync signal Port K5: Output port Signal for LCD driver Port K6: Output port Signal for LCD driver Port K7: Output port Signal for LCD driver Port L0 to L7: Output port Data bus for LCD driver: LD0 to LD7 Port M1: Output port Timer A1 output: Output pin for 8 bit timer 1 Melody / Alarm output pin Port M2: Output port Alarm output from RTC Melody / Alarm output pin (inverted) Port M7: Output port External power supply control output: Pin to control ON/OFF for external power supply. In stand-by mode, outputs "L" level In other than stand-by mode, outputs "H" level Port N: I/O port Key output 0 to 7: Key scan strobe pin (programmable Open-drain output) Port P1: I/O port Timer A3 output: Output pin for 8 bit timer 3 Port P2: I/O port Timer A5 output: Output pin for 8 bit timer 5 Port P3: I/O port (Schmitt-input) Interrupt request pin 5: Interrupt request pin with programmable rising/falling edge Timer A7 output: Output pin for 8 bit timer 7 Port P4: I/O port (Schmitt-input) Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Timer B0 input: Input pin for 16 bit timer 0 Port P5: I/O port (Schmitt-input) Interrupt request pin 7: Interrupt request pin with programmable rising/falling edge Timer B1 input: Input pin for 16 bit timer 1 Port P6: I/O port Timer B0 output: Output pin for 16 bit timer 0 Port P7: I/O port Timer B1 output: Output pin for 16 bit timer 1 Port R0: I/O port Data input pin for SD card Port R1: I/O port Data output pin for SD card Port R2: I/O port Chip select signal for SD card 1 1 Output Output Output PM7 PWE PN0 to PN7 KO0 to KO7 PP1 TA3OUT PP2 TA5OUT PP3 INT5 TA7OUT PP4 INT6 TB0IN0 PP5 INT7 TB1IN0 PP6 TB0OUT0 PP7 TB1OUT0 PR0 SPDI PR1 SPDO PR2 SPCS 1 Output I/O Output I/O Output I/O Output I/O Input Output I/O 8 1 1 1 1 Input Input I/O 1 Input Input Output Output Output Output I/O Input I/O Output I/O Output 1 1 1 1 1 92CF26A-11 2007-11-21 TMP92CF26A Table 2.2.1 Pin names and functions (5/6) Pin name PR3 SPCLK PT0 to PT7 LD8 to LD15 PU0 to PU4,PU6 LD16 to LD20,LD22 Number of Pins 1 8 6 1 I/O I/O Output I/O Output I/O Output I/O Output I/O Output Output I/O Output I/O I/O Output I/O I/O I/O I/O I/O Output Output Output I/O Input I/O I/O Input I/O Input I/O Input I/O Input I/O Input I/O Input I/O Output I/O Output Port R3: I/O port Clock output pin for SD card Port T0 to T7: I/O port Data bus for LCD driver: LD8 to LD15 Port U0 to U4 , U6: I/O port Functions Data bus for LCD driver: LD16 to LD20, LD22 Port U5: I/O port Data bus for LCD driver: LD21 Port U7: I/O port Data bus for LCD driver: LD23 Output pin for Debug mode Port V0: I/O port Clock I/O for serial 0 Port V1: I/O port Port V2: I/O port Port V3 to V4: Output port Port V6: I/O port Send/receive data at I C mode Port V7: I/O port Input/output clock at I C mode Port W0 to W7: I/O port Port X4: Output port Internal clock output pin Output pin for LCD driver Port X5: I/O port Clock input pin for USB Port X7: I/O port Port Z0: I/O port (Schmitt-input) Input pin for Debug mode Port Z1: I/O port (Schmitt-input) Input pin for Debug mode Port Z2: I/O port (Schmitt-input) Input pin for Debug mode Port Z3: I/O port (Schmitt-input) Input pin for Debug mode Port Z4: I/O port (Schmitt-input) Input pin for Debug mode Port Z5: I/O port (Schmitt-input) Input pin for Debug mode Port Z6: I/O port (Schmitt-input) Output pin for Debug mode Port Z7: I/O port (Schmitt-input) Output pin for Debug mode 2 2 PU5 LD21 PU7 LD23 EO_TRGOUT PV0 SCLK0 PV1 PV2 PV3 to PV4 PV6 SDA PV7 SCL PW0 to PW7 PX4 CLKOUT LDIV PX5 X1USB PX7 PZ0 EI_PODDATA PZ1 EI_SYNCLK PZ2 EI_PODREQ PZ3 EI_REFCLK PZ4 EI_TRGIN PZ5 EI_COMRESET PZ6 EO_MCUDATA PZ7 EO_MCUREQ 1 1 1 1 2 1 1 8 1 1 1 1 1 1 1 1 1 1 1 92CF26A-12 2007-11-21 TMP92CF26A Table 2.2.1 Pin names and functions (6/6) Pin name Number of Pins 2 1 I/O USB-data connecting pin Functions D+, D- CLKOUT I/O Output Connect pull-up(DVCC3A) or pull-down resistor to both pins to avoid through current when USB is not in use. Internal clock output pin Operation mode; Fix to AM1 = "0",AM0 = "1" for 16 bit external bus starting AM1,AM0 2 Input Fix to AM1 = "1",AM0 = "0" is prohibit to set Fix to AM1 = "1",AM0 = "1" for BOOT (32 bit internal Mask ROM) starting Fix to AM1 = "0",AM0 = "0" is prohibited to set DBGE X1/X2 XT1/XT2 RESET VREFH VREFL AVCC AVSS DVCC3A DVCC3B DVCC1A DVCC1B DVSSCOM DVCC1C DVSS1C Dummy4-1 1 2 2 1 1 1 1 1 12 1 5 1 12 1 1 4 Input I/O I/O Input Input Input - - - - - - - - - - Input pin in debug mode (This pin is set to "Debug mode" by input "0" ) High-frequency oscillator circuit connection pin Low-frequency oscillator circuit connection pin Reset: Initialize TMP92CF26A (Schmitt-input , with pull-up resistor) Pin for reference voltage input to AD converter(H) Pin for reference voltage input to AD converter(L) Power supply pin for AD converter GND pin for AD converter (0V) Power supply pin for peripheral I/O-A (All DVCC3A pins should be connected to the power supply pin ) Power supply pin for peripheral I/O-B (All DVCC3B pins should be connected to the power supply pin ) Power supply pin for internal logic-A (All DVCC1A pins should be connected to the power supply pin ) Power supply pin for internal logic-B (Keep the voltage DVCC1A level ) GND pin (0V) (All DVSS pins should be connected to GND(0V) ) Power supply pin for High speed oscillator (Keep the voltage DVCC1A level ) GND pin (0V) (DVSS1C pin should be connected to GND(0V) ) Dummy1 and Dummy2, Dummy3 and Dummy4 are shorted in package (These pins are not connected with internal LSI chip ) Table 2.2.2 shows the range of operational voltage for power supply pins. Table 2.2.2 the range of operational voltage for power supply pins Power supply pin DVCC1A DVCC1B DVCC1C DVCC3A DVCC3B AVCC 3.0V~3.6V 1.4V~1.6V Range of operational voltage 92CF26A-13 2007-11-21 TMP92CF26A 3. Operation This section describes the basic components, functions and operation of the TMP92CF26A. 3.1 CPU The TMP92CF26A contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process Instructions more quickly. The following is an outline of the CPU: Table 3.1.1Outline of TMP92CF26A Parameter Width of CPU Address Bus Width of CPU Data Bus Internal Operating Frequency Minimum Bus Cycle Internal RAM Internal Boot ROM Internal I/O TMP92CF26A 24-bit 32-bit Max 80MHz 1-clock access (12.5ns at 80MHz) 32-bit 2-1-1-1 clock access 32 bit 2-clock access 8-bit, INTC,SDRAMC, 2-clock access MEMC,LCDC, TSI,PORT,PMC 16-bit, 2-clock access 32-bit, 2-clock access 32-bit, 1-clock access 8-bit, 5 to 6-clock access MMU,USB, NDFC,SPIC,DMAC IS MAC 2 External memory (SRAM, MASKROM etc.) External memory (SDRAM) External memory (NAND FLASH) Minimum Instruction Execution Cycle Conditional Jump Instruction Queue Buffer Instruction Set CPU mode Micro DMA Hardware DMA TMRA,TMRB, SIO,RTC, MLD/ALM, SBI CGEAR,ADC,WDT 8/16-bit 2-clock access (waits can be inserted) 16-bit 1-clock access 8/16-bit 2-clock access (waits can be inserted) 1-clock (12.5ns at 80MHz) 2-clock (25.0ns at 80MHz) 12-byte Compatible with TLCS-900/L1 (LDX instruction is deleted) Maximum mode only 8-channel 6-channel 92CF26A-14 2007-11-21 TMP92CF26A 3.1.2 Reset Operation When resetting the TMP92CF26A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input Low for at least 20 system clocks (32s at X1=10MHz). At reset, since the clock doublers (PLL0) is bypassed and the clock-gear is set to 1/16, the system clock operates at 625 kHz(X1=10MHz). When the Reset has been accepted, the CPU performs the following. CPU internal registers do not change when the Reset is released. * Sets the Stack Pointer (XSP) to 00000000H. * Sets bits When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows. * Initializes the internal I/O registers as table of "Special Function Register" in Section 5. Note1: This LSI builds in RAM internally. However, the data in internal RAM may not be held by Reset operation. After reset, initialize the data in internal RAM. Note2: This LSI builds in PMC function (for reducing stand-by current by blocking the power supply of DVCC1A and DVCC1C). However, if executing reset operation without supplying DVCC1A and DVCC1C, the current may flow to internal. When reset this LSI, supply the power of DVCC1A and DVCC1C first and wait until the power supply stabilizes. Figure 3.1.1 shows reset timing chart. Figure 3.1.2 shows the example of order of supplying power and the timing of releasing reset. 92CF26A-15 2007-11-21 fSYS Sampling Sampling RESET fSYSx(15.516.5) Clock 0FFFF00H A23A0 CS0,1, 3 CS2 D0D15 DATA-IN DATA-IN Read Figure 3.1.1 TMP92CF26A Reset timing chart 92CF26A-16 RD SRxxB (After reset is released, it is started from 1 wait read cycle) D0D15 DATA-OUT Write WRxx SRWR SRxxB TMP92CF26A 2007-11-21 : High-Z TMP92CF26A This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. When Powering on Power Cut Mode (PMC) When Powering off DVCC1A 1.5V Power DVCC1B DVCC1C 1.5-V rails should be turned on first, followed by the 3.3-V rails. Power should rise and stabilizes within 100 ms. Power should fall and stabilizes within 100 ms. 3.3-V rails should be turned off first, followed by the 1.5-V rails. 3.3V Power DVCC3A DVCC3B AVCC High-frequency Oscillation Stabilizing Time 20 system clock cycles RESET PWE terminal Note1: Although it is possible to turn on or off the 1.5-V and 3.3-V power supply rails simultaneously, it may cause external pins to temporarily become unstable. Therefore, if there is any possibility that this would affect peripheral devices connected with the TMP92CF26A, external power supplies should be turned on or off while the internal power supplies are stable, as indicated by the heavy lines in the diagram above. Note2: In the power-on sequence, the 3.3-V power supply rails must not be turned on before the ones of 1.5-V . In the power -off sequence, the 3.3-V power supply rails must not be turned off after the ones of 1.5-V. Figure 3.1.2 Power on Reset Timing Example 92CF26A-17 2007-11-21 TMP92CF26A 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin RESET AM1 0 1 AM0 1 0 Operation Mode DBGE 0 1 0 1 0 1 0 1 Debug mode 16-bit external bus starting Test mode (Prohibit to set) Test mode (Prohibit to set) BOOT(32-bit internal-MROM ) starting (BOOT mode) Test mode (Prohibit to set) 1 1 0 0 92CF26A-18 2007-11-21 TMP92CF26A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CF26A. 000000H Internal I/O (8 Kbyte) Direct area(n) 64Kbyte area (nn) 000100H 001FF0H 002000H 010000H 021FFFH Don't access area 046000H (Internal Back Up RAM 16kbyte) Internal RAM (128 Kbyte) 04A000H External memory 16Mbyte area (R) F00000H F10000H External memory Provisional Emulator Control Area (64kbyte) (-R) (Note1) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 Byte) (Note2) ( = Internal area ) Figure 3.2.1 Memory Map Note1: The Provisional emulator control area, mapped F00000H to F0FFFFH after reset, is for a Debug mode use and so is not available Note2: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved as internal area. 92CF26A-19 2007-11-21 TMP92CF26A 3.3 Clock Function and Standby Function The TMP92CF26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise reduction circuits. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller 3.3.5 Noise reduction circuits 3.3.7 Standby controller 92CF26A-20 2007-11-21 TMP92CF26A The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/16) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) instruction interrupt instruction interrupt (a) release Reset PLL-OFF mode (fOSCH/gear value) instruction interrupt STOP mode (Stops all circuits) PLL-OFF mode transition figure Reset (fOSCH/16) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) instruction interrupt instruction interrupt instruction interrupt instruction interrupt (b) release Reset instruction PLL-OFF mode interrupt /gear value) (f OSCH STOP mode (Stops all circuits) Instruction (Note) PLL-ON mode ((12 or 16)xfOSCH/gear value) PLL-OFF , PLL-ON mode transition figure Note 1: When shifting from PLL-ON mode to PLL-OFF mode, execute the following setting in the same order. (1) Change CPU clock (Set "0" to PLLCR0 Figure 3.3.1 System clock block diagram The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 92CF26A-21 2007-11-21 TMP92CF26A 3.3.1 Block diagram of system clock SYSCR0 fc/16 /2 /2 /4 /8 /16 /4 T0 T0TMR /2 /8 SYSCR0 fPLL fc/8 /2 fIO X1 X2 High frequency Oscillator circuit fOSCH SYSCR1 Clock gear PLLCR0 /5 Clock Doubler1 (PLL1)x 24 X1USB fPLLUSB fUSB fSYS fio T0TMR TMRA0:7,TMRB0:1 Prescaler CPU RAM Interrupt Controller SIO0 LCDC Memory Controller NAND-Flash Controller IS TSI SPIC 2 T0 I/O ports Prescaler fPLL SDRAMC SBI Prescaler DMAC MAC RTC fs MLD/ALM ADC WDT fUSB USB Figure 3.3.2 Block Diagram of System clock 92CF26A-22 2007-11-21 TMP92CF26A TMP92CF26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don't connect oscillator more than 10MHz. When clock is input by using external oscillator, range of input frequency is 6 to 10MHz. Don't input the clock over 10MHz. Table 3.3.1 Setting example for fOSCH High frequency: fOSCH (a) USB in use, with PLL (PLL0 ON/PLL1 ON) (b) USB not in use, with PLL (PLL0 ON/PLL1 OFF) (c) USB not in use, without PLL (PLL0 OFF/PLL1 OFF) 10.0 MHz Max 10.0 MHz Max 10.0 MHz System clock: fSYS Max 80 MHz Max 80 MHz Max 10 MHz System clock: fSYS Max 60 MHz Max 60 MHz Max 10 MHz USB clock: fUSB 48 MHz - - Note: When using USB, the high-frequency oscillator should be 10.0 MHz. 92CF26A-23 2007-11-21 TMP92CF26A 3.3.2 SFR 7 SYSCR0 (10E0H) bit Symbol Read/write Reset State Function 6 XTEN 1 Low -frequency oscillator circuit (fs) 5 USBCLK1 R/W 0 4 USBCLK0 0 3 2 WUEF R/W 0 Warm-up Timer 0: Write Don't care Note3 1: Write start timer 0: Read end warm-up 1: Read do not end warm-up 1 0 PRCK R/W 0 Select Prescaler clock 0: fSYS/2 1: fSYS/8 Select the clock of USB(fUSB) 00:Disable 01: Reserved 10: X1USB 0: Stop 1: Oscillation 11: fPLLUSB 7 SYSCR1 (10E1H) bit Symbol Read/write Reset State Function 6 5 4 3 2 GEAR2 1 1 GEAR1 R/W 0 0 GEAR0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: Reserved 110: Reserved 111: Reserved 7 SYSCR2 (10E2H) bit Symbol Read/write Reset State Function - 0 Always write "0" 6 CKOSEL 0 Select CLKOUT 0: fSYS 1: fS 5 4 3 HALTM1 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 1 1 0 WUPTM1 WUPTM0 R/W 1 0 Warm-Up Timer 00: Reserved 01: 28/inputted frequency 10:214/inputted frequency 11:216/inputted frequency Note1: The unassigned registers, SYSCR0 Figure 3.3.3 SFR for system clock 92CF26A-24 2007-11-21 TMP92CF26A 7 EMCCR0 Bit symbol (10E3H) Read/Write Reset State Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 5 4 3 - 2 EXTIN 0 1: External clock 1 0 0 Always write "0". DRVOSCH DRVOSCL R/W 1 1 fc oscillator fs oscillator drive ability drive ability 1: NORMAL 0: WEAK 1: NORMAL 0: WEAK EMCCR1 Bit symbol (10E4H) Read/Write Reset State Function EMCCR2 Bit symbol (10E5H) Read/Write Reset State Function Switch the protect ON/OFF by writing the following to 1 -KEY,2 -KEY st 1 -KEY: write in sequence EMCCR1=5AH,EMCCR2=A5H nd 2 -KEY: write in sequence EMCCR1=A5H,EMCCR2=5AH st nd Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 Figure 3.3.4 SFR for system clock 92CF26A-25 2007-11-21 TMP92CF26A 7 PLLCR0 (10E8H) bit symbol Read/Write Reset State Function 6 FCSEL R/W 0 Select fc-clock 0 : fOSCH 1 : fPLL 5 LUPFG R 0 Lock-up timer Status flag 0 : not end 1 : end 4 3 2 1 0 Note: Ensure that the logic of PLLCR0 7 PLLCR1 (10E9H) bit symbol Read/Write Reset State Function PLL0 0 PLL0 for CPU 0: Off 1: On 6 PLL1 R/W 0 PLL1 for USB 0: Off 1: On 5 LUPSEL 0 Select stage of Lock up counter 0: 12 stage (for PLL0) 1:13 stage (for PLL1) 4 3 2 1 0 PLLTIMES R/W 0 Select the number of PLL 0: x12 1: x16 Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) bit symbol Read/Write System Reset State Hot Reset State Function Px7D 6 Px6D 5 Px5D 4 Px4D R/W 3 Px3D 2 Px2D 1 Px1D 0 Px0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Output/Input buffer drive-register for standby-mode (Purpose and using) * * * * * * This register is used to set each pin-status at stand-by mode. All ports have registers of the format shown above. ("x" indicates the port name.) For each register, refer to 3.5 Function of Ports. Before "HALT" instruction is executed, set each register pin-status. They will be effective after the CPU has executes the "HALT" instruction. This is the case regardless of stand-by modes (IDLE2, IDLE1 or STOP). This is the case regardless of using PMC function. For details, refer to PMC section. The Output/Input buffer control table is shown below. OE 0 0 1 1 PxnD 0 1 0 1 Output buffer OFF OFF OFF ON Input buffer OFF ON OFF OFF Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note2: "n" in PxnD denotes the bit number of PORTx. Figure 3.3.6 SFR for Drive register 92CF26A-26 2007-11-21 TMP92CF26A 3.3.3 System clock controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. SYSCR0 SYSCR1 EQU LD LD X: don't care 10E1H (SYSCR1),XXXXX001B (DUMMY),00H ; Changes system clock fSYS to fc/2 Dummy instruction (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 (Example) SYSCR1 EQU LD LD 10E1H (SYSCR1),XXXXX010B (DUMMY),00H ; ; Changes fSYS to fc/4 Dummy instruction Instruction to be executed after clock gear changed 92CF26A-27 2007-11-21 TMP92CF26A 3.3.4 Clock doubler (PLL) PLL0 outputs the fPLL clock signal, which is 12 or 16 times as fast as fOSCH. A low-speed frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, so setting to PLLCR0 and PLLCR1-register is needed before use. As with an oscillator, this circuit requires time to stabilize. This is called the lock-up time and it is measured by a 12-stage binary counter. Lock-up time is about 0.41ms at fOSCH = 10MHz. PLL (PLL1) which is special for USB is built in. Lock-up time is about 0.82ms at fOSCH = 10MHz measured by 13-stage binary counter. Note1: Input frequency range for PLL The input frequency range (High frequency oscillation) for PLL is as follows: fOSCH = X to X MHz (Vcc = 1.4 to 1.6V) Note2: PLLCR0 Table 3.3.2 shows the frequency of fSYS when using PLL and clock gear at fOSCH =10MHz. Table 3.3.2 The frequency of fSYS at fOSCH =10MHz fOSCH 10MHz fPLL fOSCH 10MHz x12 120MHz x16 160MHz Frequency of fSYS fc 10MHz 60MHz 80MHz fc/2 5MHz 30MHz 40MHz fc/4 2.5MHz 15MHz 20MHz fc/8 1.25MHz 7.5MHz 10MHz fc/16 625KHz 3.75MHz 5MHz 92CF26A-28 2007-11-21 TMP92CF26A The following is an example of settings for PLL0-starting and PLL0 stopping. (Example-1) PLL0-starting PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD X: Don't care Counts up by fOSCH 10E8H 10E9H (PLLCR1),1XXXXXXXXB 5,(PLLCR0) Z,LUP (PLLCR0), X1XXXXXXB ; ; ; ; Enables PLL0 operation and starts lock up. Detects end of lock-up Changes fc from 10 MHz to 60 MHz. During lock-up After lock-up (Example-2) PLL0-stopping PLLCR0 PLLCR1 EQU EQU LD LD X: Don't care 10E8H 10E9H (PLLCR0),X0XXXXXXB (PLLCR1),0XXXXXXXB ; ; Changes fc from 60 MHz to10 MHz. Stop PLL Note: PLL1 operates as well. 92CF26A-29 2007-11-21 TMP92CF26A Limitations on the use of PLL0 1. When stopping PLL operation during PLL0 use, execute the following settings in the same order. LD LD X: Don't care (PLLCR0),X0XXXXXXB (PLLCR1),0XXXXXXXB ; ; Change the clock fPLL to fOSCH Stop PLL0 2. When shifting to STOP mode during PLL use, execute the following settings in the same order. LD LD LD HALT X: Don't care (SYSCR2),XXXX01XXB (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB ; ; ; ; Set the STOP mode Change the system clock fPLL to fOSCH Stop PLL0 Shift to STOP mode Examples of settings are shown below: (1) Start Up / Change Control (OK) High frequency oscillator operation mode(fOSCH )PLL0 start up PLL0 use mode (fPLL ) LD LUP: BIT JR LD X: Don't care (PLLCR1), 1XXXXXXXB 5,(PLLCR0) Z,LUP (PLLCR0), X1XXXXXXB ; ; ; ; Check for lock up end flag Change the system clock fOSCH to fPLL PLL0 start up / lock up start (2) Change / Stop Control (OK) PLL0 use mode (fPLL ) High frequency oscillator operation mode(fOSCH ) PLL0 Stop LD LD X: Don't care (PLLCR0),X0XXXXXXB (PLLCR1),0XXXXXXXB ; ; Change the system clock fPLL to fOSCH Stop PLL0 (OK) PLL0 use mode (fPLL ) Set the STOP mode High frequency oscillator operation mode (fOSCH) PLL stop HALT(High frequency oscillator stop) LD LD LD HALT X: Don't care (SYSCR2),XXXX01XXB (PLLCR0),X0XXXXXXB (PLLCR1),0XXXXXXXB ; ; ; ; Set the STOP mode (This command can be executed before use of PLL0) Change the system clock fPLL to fOSCH Stop PLL0 Shift to STOP mode (NG) PLL0 use mode (fPLL) Set the STOP mode HALT(High frequency oscillator stop) LD HALT X: Don't care (SYSCR2),XXXX01XXB ; ; Set the STOP mode (This command can be executed before use of PLL0) Shift to STOP mode 92CF26A-30 2007-11-21 TMP92CF26A 3.3.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) Runaway prevention using SFR protection register These are set in EMCCR0 to EMCCR2 registers. (1) Reduced drivability for high-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Clock diagram) fOSCH C1 Resonator X1 pin Enable oscillation EMCCR0 C2 X2 pin (Setting method) The drivability of the oscillator is reduced by writing"0" to EMCCR0 Note: This function (EMCCR0 92CF26A-31 2007-11-21 TMP92CF26A (2) Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 Resonator EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 Note: Do not write EMCCR0 92CF26A-32 2007-11-21 TMP92CF26A (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (Memory controller, MMU) which prevent fetch operations.. Runaway error handling is also facilitated by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, MEMCR0, CSTMGCR, WRTMGCR, RDTMGCR0 RDTMGCR1, BROMCR 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, LOCALESX/ESY/ESZ, LOCALEDX/EDY/EDZ, LOCALOSX/OSY/OSZ, LOCALODX/ODY/ODZ 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0,PLLCR1 5. PMC PMCCTL (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st-KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2 Protection state can be confirmed by reading EMCCR0 92CF26A-33 2007-11-21 TMP92CF26A 3.3.6 Standby controller (1) HALT Modes and Port Drive-register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2 PxDR bit symbol (xxxxH) Read/Write System Reset State Hot Reset State Function Px7D 6 Px6D 5 Px5D 4 Px4D R/W 3 Px3D 2 Px2D 1 Px1D 0 Px0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Output/Input buffer drive-register for standby-mode (Purpose and using) * * * * This register is used to set each pin-status at stand-by mode. All ports have this registers of the format shown above ("x" indicates the port-name.) For each register, refer to 3.5 Function of Ports. Before "HALT" instruction is executed, set each register pin-status. They will be effective after the CPU has executed the "HALT" instruction. * This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). * This is the case regardless of using PMC function. For details, refer to PMC section. The Output/Input-buffer control table is shown below. OE 0 0 1 1 PxnD 0 1 0 1 Output buffer OFF OFF OFF ON Input buffer OFF ON OFF OFF Note1: OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note2: "n" in PxnD denotes the bit number of PORTx. The subsequent actions performed in each mode are as follows: a. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.3 shows the registers setting operation during IDLE2 mode. Table 3.3.3 SFR setting operation during IDLE2 mode Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 TMRB1 SIO0 SBI A/D converter WDT SFR TA01RUN b. IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to operate. c. STOP: All internal circuits stop operating. 92CF26A-34 2007-11-21 TMP92CF26A The operation of each of the different Halt Modes is described in Table 3.3.4. Table 3.3.4 I/O operation during Halt Modes HALT Mode SYSCR2 CPU, MAC I/O ports TMRA, TMRB SIO,SBI A/D converter WDT I2S, LCDC, SDRAMC, Interrupt controller, SPIC, DMAC, NDFC, USB RTC, MLD IDLE2 11 IDLE1 10 Stop Depends on PxDR register setting STOP 01 Available to select Operation block Stop Block Operate Operate (2) How to release the Halt mode These HALT states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination of the states of the interrupt mask register 92CF26A-35 2007-11-21 TMP92CF26A Table 3.3.5 Source of Halt state clearance and Halt clearance operation Status of Received Interrupt HALT mode INTWDT INT0 to 5 (Note1) INTKEY INTUSB INT6 to 7(PORT) (Note1) INT6 to 7(TMRB) Interrupt x Interrupt Enabled (interrupt level) (interrupt mask) IDLE2 IDLE1 x Interrupt Disabled (interrupt level) < (interrupt mask) IDLE2 - STOP x *1 IDLE1 - STOP - *1 *2 Source of Halt state clearance x *1 *2 x *1 x x x x x x INTALM, INTRTC INTTA0 to 7, INTTP0 INTTB00 to 01, INTTB10 to 11 INTRX,INTTX, INTSBI INTI2S0 to 1, INTLCD, INTAD, INTADHP INTSPIRX,INTSPITX INTRSC, INTRDY INTDMA0 to 5 RESET x x x x x Reset initializes the LSI : After clearing the Halt mode, CPU starts interrupt processing. : After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction. x: Cannot be used to release the halt mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This combination is not available. *1: Release of the HALT mode is executed after warm-up time has elapsed. *2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the construction of low power dissipation systems. However, the method of use is limited as below. * Shift to IDLE1 mode : Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is "1" ( SUSPEND state ) * Release from IDLE1 mode : Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request) Release Halt state by INT_URST_STR or INT_URST_END request(RESET request) Note: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. 92CF26A-36 2007-11-21 TMP92CF26A (Example - releasing IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (PCFC), 02H (IIMC0), 00H (INTE0), 06H 5 (SYSCR2), 28H ; Sets PC1 to INT0 interrupt. ; Select INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets CPU interrupt level to 5. ; Sets Halt mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine. RETI 820FH LD XX, XX 92CF26A-37 2007-11-21 TMP92CF26A (3) Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt. X1 A0~A23 D0~D31 RD Data Data WR Interrupt for releasing Halt IDLE2 mode Figure 3.3.7 Timing chart for IDLE2 Mode Halt state cleared by interrupt b. IDLE1 Mode In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock stops. In the Halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (i.e. restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 Mode Halt state by an interrupt. X1 A0~A23 D0~D31 RD Data Data WR Interrupt for releasing Halt IDLE1 mode Figure 3.3.8 Timing chart for IDLE1 Mode Halt state cleared by interrupt 92CF26A-38 2007-11-21 TMP92CF26A c. STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt. Warm-up time X1 A0~A23 D0~D31 RD Data Data WD Interrupt for releasing Halt STOP mode Figure 3.3.9 Timing chart for STOP Mode Halt state cleared by interrupt Table 3.3.6 Example of warming-up time after releasing STOP-mode @fOSCH =10 MHz SYSCR2 25.6 s 8 10 (214) 1.6384 ms 11 (216) 6.5536 ms 92CF26A-39 2007-11-21 TMP92CF26A Table 3.3.7 Input Buffer State Table Input Buffer State Port Name Input Function Name During Reset When Used as function Pin D0-D7 P10-P17 P60-P67 P71-P74 P75 P76 P90 P91 P92 P96 *1 P97 PA0-PA7 *1 PC0 PC1 PC2 PC3 PC4-PC7 PF0-PF5 PG0-PG2 PG4,PG5 *2 PG3 *2 PJ5-PJ6 PN0-PN7 PP1-PP2 PP3 PP4 PP5 PR0 PR1-PR3 PT0-PT7 PU0-PU4, PU6,PU7 PU5 PV0-PV2 PV6-PV7 PW0-PW7 PX5 PX7 CTS0 When the CPU is operating When Used as Input port - In HALT mode (IDLE2/1/STOP) function Pin OFF Input port - OFF function Pin Input port - When Used as When Used as When Used as When Used as D0-D7 D8-D15 - - NDR/ W WAIT OFF 16bit Start OFF Boot Start ON 16bit Start OFF Boot Start ON ON upon external read - - ON - ON - - ON - ON ON - ON - - OFF - OFF - - RXD0 ,SCLK0 - KI0-KI7 INT0 INT1,TA0IN INT2 INT3,TA2IN - - - ADTRG INT4 ON - ON ON OFF - - ON - ON upon port read - - ON - - - ON - OFF OFF OFF - - - INT5 INT6,TB0IN0 INT7,TB1IN0 SPDI - - - - - SDA, SCL - X1USB - EI_PODDATA, EI_SYNCLK, EI_PODREQ, EI_REFCLK, EI_TRGIN, EI_COMRESET - - - - - - ON: The buffer is always turned on. A current flows through the input buffer if the input pin is not driven. IDLE2/DLE1: ON *1: Port having a pull-up/pull-down resistor. Always ON - - ON ON ON ON ON OFF - - - ON ON OFF PZ0-PZ5 ON PZ6-PZ7 DBGE - D+, DRESET AM0,AM1 X1,XT1 *2: AIN input does not cause a current to flow through the buffer. OFF: The buffer is always turned off. - : Not applicable 92CF26A-40 2007-11-21 TMP92CF26A Table 3.3.8 Output buffer State Table (1/2) Output Buffer State Port Name Output Function Name During Reset When Used as function Pin D0-7 P10-17 P40-P47 P50-P57 P60-67 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P96 P97 PC0-PC3 PC4 PC5 PC6 PC7 PF0 PF1 PF2 PF3 PF4 PF5 PF7 PG2 PG3 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PL0-PL7 CS 2 When the CPU is operating When Used as Output port - ON In HALT mode (IDLE2/1/STOP) function Pin OFF Output port - ON function Pin Output port - When Used as When Used as When Used as When Used as D0-D7 D8-D15 A0-A7 A8-A15 A16-A23 RD OFF 16bit Start OFF Boot Start OFF ON 16bit Start ON Boot Start OFF ON ON upon external write OFF ON ON WRLL WRLU , NDRE , NDWE OFF EA24 EA25 R/ W - CS0 - ON - ON - OFF CS1 , SDCS , CSZA CSZB CSZC SDCS CS3 , CSXA ON ON ON OFF CSZD , ND0CE , - ND1CE CSXB TXD0 OFF - ON - - ON - - OFF - SCLK0 PX PY - EA26 EA27 EA28 KO8 I2S0CKO I2S0DO I2S0WS I2S1CKO I2S1DO I2S1WS SDCLK MX MY SDRAS SDCAS SDWE - - - OFF ON ON OFF ON OFF - - - , SRLLB , SRLUB , SRWR ON ON ON OFF SDLLDQM SDLUDQM NDALE NDCLE SDCKE LCP0 LLOAD LFR LVSYNC LHSYNC LGOE0 LGOE1 LGOE2 LD0-LD7 ON ON ON OFF OFF 92CF26A-41 2007-11-21 TMP92CF26A Table 3.3.9 Output buffer state table (2/2) Output Buffer State Port Name Output Function Name During Reset When the CPU is operating When Used as function Pin PM1 PM2 PM7 PN0-PN7 PP1 PP2 PP3 PP4-PP5 PP6 PP7 PR0 PR1 PR2 PR3 PT0-PT7 PU0-PU6 PU7 PV0 PV1 PV2 PV3-PV4 PV6 PV7 PW0-PW7 PX4 PX5 PX7 PZ0-PZ5 PZ6-PZ7 D+, D- X2 XT2 MLDALM,TA1OUT MLDALM In HALT mode (IDLE2/1/STOP) function Pin Output port function Pin Output port When Used as Output port When Used as When Used as When Used as When Used as , ALARM ON ON OFF - ON ON - - ON - - OFF - ON OFF PWE KO0-KO7 TA3OUT TA5OUT TA7OUT - TB0OUT0 TB1OUT0 - SPDO SPCS SPCLK LD8-LD15 LD16-LD22 LD23 EO_TRGOUT SCLK0 - - - SDA SCL - CLKOUT, LDIV - - - EO_MCUDATA, EO_MCUREQ - - Always ON - OFF OFF ON ON ON/OF depend on USBC operation - - ON OFF ON ON - ON ON - ON - - OFF ON ON ON ON OFF OFF ON OFF - OFF - OFF - ON IDLE2/1:ON, STOP: output "H" IDLE2/1:ON, STOP: output "HZ" ON: The buffer is always turned on. When the bus is released, however, output buffers for some pins are turned off. OFF: The buffer is always turned off. - : Not applicable *1: Port having a pull-up/pull-down resistor. 92CF26A-42 2007-11-21 TMP92CF26A 3.4 Boot ROM The TMP92CF26A contains boot ROM for downloading a user program, and supports two kinds of downloading methods. 3.4.1 Operation Modes The TMP92CF26A has two operation modes: MULTI mode and BOOT mode. The operation mode is selected according to the AM1 and AM0 pin levels when RESET is asserted. (1) MULTI mode: (2) BOOT mode: After reset, the CPU fetches instructions from external memory and executes them. After reset, the CPU fetches instructions from internal boot ROM and executes them. The boot ROM loads a user program into internal RAM from USB, or via UART, and then branches to the internal RAM. In this way the user program starts boot operation. Table 3.4.2 shows an outline of boot operation. Table 3.4.1 Operation Modes Mode Setting Pins RESET Operation Mode MULTI TEST (Setting prohibited) BOOT (Start from internal boot ROM) TEST (Setting prohibited) Start from external 16-bit bus memory AM1 0 1 1 0 AM0 1 0 1 0 Table 3.4.2 Outline of Boot Operation Name (a) (b) Priority Source 1 2 PC (UART) PC (USB_HOST) Loading I/F UART USB Destination Internal RAM Operation after Loading Branch to internal RAM 92CF26A-43 2007-11-21 TMP92CF26A 3.4.2 Hardware Specifications of Internal Boot ROM (1) Memory map Figure 3.4.1 shows a memory map of BOOT mode. The boot ROM incorporated in the TMP92CF26A is an 8-Kbyte ROM area mapped to addresses 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and the above area is mapped as an external area. 000000H Internal I/O 001FF0H 002000H 010000H 021FFFH Internal RAM (128 Kbytes) 046000H 04A000H (Internal Backup RAM 16 Kbytes) 3FE000H Internal Boot ROM (8 Kbytes) 3FFF00H 400000H (B) Reset/Interrupt (Note) Vector Area (256 bytes) FFFF00H FFFFFFH Note: BROMCR (A) Reset/Interrupt (Note) Vector Area (256 bytes) Figure 3.4.1 Memory Map of BOOT Mode (2) Switching the boot ROM area to an external area After the boot sequence is executed in BOOT mode, an application system program may start running without a reset being asserted. In this case, it is possible to switch the boot ROM area to an external area. 92CF26A-44 2007-11-21 TMP92CF26A 3.4.3 Outline of Boot Operation The method for downloading a user program can be selected from two types: from UART, or via USB. After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2. Regardless of the downloading method used, the boot program downloads a user program into the internal RAM and then branches to the internal RAM. Figure 3.4.3 shows how the boot program uses the internal RAM (common to all the downloading methods). Start Yes RESUME check PMCCTL (b) UART check No No Yes Download via UART USB check Yes Download via USB Branch to internal RAM 3000h Branch to internal RAM 46000h Note 1: To download a user program via USB, a USB device driver and special application software are needed on the PC. Note 2: To download a user program via UART, special application software is needed on the PC. Note 3: The (a), (b) in the above flowchart indicate points where the settings of external port pins are changed. For details, see Table 3.4.3. Figure 3.4.2 Flowchart for Internal Boot ROM Operation 92CF26A-45 2007-11-21 TMP92CF26A 002000H Work Area for Boot Program (4 Kbytes) 003000H Download Area for User Program (124 Kbytes) 021FFFH 046000H Work Area for User Program (14 Kbytes) 049800H Stack Area for Boot program (2K bytes) 049FFFH Figure 3.4.3 How the Boot Program Uses Internal RAM 92CF26A-46 2007-11-21 TMP92CF26A (1) Port settings Table 3.4.3 shows the port settings by the boot program. When designing your application system, please also refer to Table 3.4.4 for recommended pin connections for using the boot program. The boot program only sets the ports shown in the table below; other ports are left as they are after reset or at startup of the boot program. Table 3.4.3 Port Settings by the Boot Program Port Name UART P90 P91 USB --- --- PU6 Function Name TXD0 RXD0 D+ D- PUCTL I/O (a) Output Input I/O I/O Output No change from after reset state (input port) No change from after reset state (input port) Set as RXD0 input pin Description (b) No change from (a) (c) Set as TXD0 output pin No change from (b) No change Set as output port No change from (b) 92CF26A-47 2007-11-21 TMP92CF26A Table 3.4.4 Recommended Pin Connections Port Name UART P90 P91 Function Name TXD0 RXD0 I/O Output Input Recommended Pin Connections for Each Download Method UART Connect to the level shifter. USB No special setting is needed for booting via USB. Add a pull-up resistor (100 krecommended) to prevent transition to UART processing. USB --- D+ I/O No special setting is needed for booting via UART. Connect to the USB connector by adding a dumping resistor (27recommended) and a programmable pull-up resistor (1.5 krecommended). When USB is not accessed, the pin level should be fixed with a resistor to prevent flow-through current. Connect to the USB connector by adding a dumping resistor (27 recommended). When USB is not accessed, the pin level should be fixed with a resistor to prevent flow-through current. This pin is used to control ON/OFF of the D+ pin's pull-up resistor. Add a switch externally so that the pull-up is turned on when "1". Reset sets this pin as an input port, so add a pull-down resistor (100k recommended). --- D- I/O If USB is not used, add a pull-up or pull-down resistor to prevent flow-through current on the D+/D- pins. PU6 PUCTL Output - Note 1: When a user program is downloaded from UART and USB is used in the system, the pull-up resistor for USB's D+ pin should not be turned on in BOOT mode. Note 2: When a user program is downloaded via USB, do not start the UART application software on the PC. Note 3: When a user program is downloaded via UART, do not connect a USB connector. Note 4: When USB is not used, the D+ and D- pins must be pulled up or down to prevent flow-through current. 92CF26A-48 2007-11-21 TMP92CF26A (2) I/O register settings Table 3.4.5 shows the I/O registers that are set by the boot program. After the boot sequence, if execution moves to an application system program without a reset being asserted, the settings of these I/O registers must be taken into account. Also note that the registers in the CPU and the internal RAM remain in the state after execution of the boot program. Table 3.4.5 I/O Register Settings by Boot Program Register Name WDMOD WDCR SYSCR0 SYSCR1 SYSCR2 PLLCR0 PLLCR1 Set Value 00H B1H 70H 00H 2CH 00H 00H or 60H Description Watchdog timer not active Watchdog timer disabled High-frequency and low-frequency oscillators operating Clock gear = 1/1 Initial value PLL clock not used Normally PLL is disabled. However, only in the case of booting via USB, PLL is activated for USB. USB interrupt level setting INTTC interrupt level setting INTEUSB INTETC01 04H 44H Note: The values to be set in the I/O registers for UART and USB are not described here. If these functions are needed in a user program, set each I/O register as necessary. 92CF26A-49 2007-11-21 TMP92CF26A 3.4.4 Downloading a User Program via UART (1) Connection example Figure 3.4.4 shows an example of connections for downloading a user program via UART (using a 16-bit NOR Flash memory device as program memory). UART 3 pins TXD Level RXD Shifter RTS PC TXD0 P90 (OUT) RXD0, P91 (IN) D+ DP82, CS2 P70, RD PJ2, SRWR CE OE WE AM0 TMP92CF26A D0 to D15 NOR Flash Memory D0 toD15 AM1 A1 to 20 A0 toA19 Note: When USB is not used, add a pull-up or pull-down resistor to the D+ and D- pins to prevent flow-through current. Figure 3.4.4 UART Connection Example (2) UART interface specifications SIO channel 0 is used for downloading a user program. The UART communication format in BOOT mode is shown below. Before booting, the PC must also be set up with the same conditions. Although the default baud rate is 9600 bps, this can be changed as shown in Table 3.4.8. Serial transfer mode: Data length Parity bit STOP bit Handshake Baud rate (default) : UART (asynchronous) mode, full-duplex : 8 bits : None : 1 bit : None : 9600 bps 92CF26A-50 2007-11-21 TMP92CF26A (3) UART data transfer format Table 3.4.6 to Table 3.4.11 show the supported frequencies, data transfer format, baud rate modification command, operation command, and version management information, respectively. Please also refer to the description of boot program operation later in this section. Table 3.4.6 Supported Frequencies (X1) 6.00 MHz 8.00 MHz 9.00 MHz 10.00 MHz Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency. Table 3.4.7 Transfer Format Byte Number to Transfer Boot ROM 2nd byte 3rd byte to 6th byte 7th byte 8th byte 9th byte 10th byte to (n - 4)th byte (n - 3)th byte (n - 2)th byte (n - 1)th byte n'th byte - RAM - Branch to user program start address "Error code x 3" means that the error code is transmitted three times. For example, if the error code is 62H, the TMP92CF26A transmits 62H three times. For error codes, see (4)-b). - - User program start command (C0H) (See Table 3.4.9.) OK: SUM (High) (See (4)-c).) OK: SUM (Low) - OK: Echo back data (C0H) Error: Error code x 3 - Baud rate modification command (See Table 3.4.8.) - User program Intel Hex format (binary) Frequency information - OK: Echo back data Error: Error code x 3 New baud rate NG: Operation stop by checksum error - - 1st byte Transfer data from PC to TMP92CF26A Matching data (5AH) Baud Rate 9600 bps Transfer data from TMP92CF26A to PC - (Frequency measurement and baud rate auto setting) OK: Echo back data (5AH) Error: No transfer Version management information (See Table 3.4.10) 92CF26A-51 2007-11-21 TMP92CF26A Table 3.4.8 Baud Rate Modification Command Baud Rate (bps) Modification Command 9600 28H 19200 18H 38400 07H 57600 06H 115200 03H Note 1: If fOSCH (oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported. Note 2: If fOSCH (oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not supported. Table 3.4.9 Operation Command Operation Command C0H Operation User program start Table 3.4.10 Version Management Information Version Information FRM1 ASCII Code 46H, 52H, 4DH, 31H Table 3.4.11 data of measuring frequency X1-X2 oscillator 6.000 8.000 9.000 frequency (MHz) 09H 0AH 08H 10.000 0BH (4) Description of the UART boot program operation The boot program receives a user program sent from the PC via UART and transfers it to the internal RAM. If the transfer ends normally, the boot program calculates SUM and sends the result to the PC before executing the user program. The execution start address is the first address received. The boot program enables users to perform customized on-board programming. When UART is used to download a user program, the maximum allowed program size is 124 Kbytes (3000H - 21FFFH). (The extended Intel Hex format is supported.) a) Operation procedure 1. Connect the serial cable. This must be done before the microcontroller is reset. 2. Set the AM1 and AM0 pins to "1" and reset the microcontroller. 3. The receive data in the 1st byte is matching data (5AH). Upon starting in BOOT mode, the boot program goes to a state in which it waits for matching data. When matching data is received, the initial baud rate of the serial channel is automatically set to 9600 bps. 4. The 2nd byte is used to echo back 5AH to the PC upon completion of the automatic baud rate setting in the 1st byte. If automatic baud rate setting fails, the boot program stops operation. 5. The 3rd through 6th bytes are used to send the version management information of the boot program in ASCII code. The PC should check that the correct version of the boot program is used. 6. The 7th byte is used to send information on the measured frequency. The PC should check that the frequency of the resonator is measured correctly. 92CF26A-52 2007-11-21 TMP92CF26A 7. The receive data in the 8th byte is baud rate modification data. The five kinds of baud rate modification data shown in Table 3.4.8 are available. Even when the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must be sent. Baud rate modification becomes effective after the echo back transmission is completed. The 9th byte is used to echo back the received data to the PC when the data received in the 8th byte is one of the baud rate modification data corresponding to the operating frequency of the microcontroller. Then, the baud rate is changed. If the received baud rate data does not correspond to the operating frequency, the boot program stops operation after sending the baud rate modification error code (62H). The receive data in the 10th to (n-4)th bytes is received as binary data in Intel Hex format. No echo back data is returned to the PC. The boot program ignores received data and does not send error code to the PC until it receives the start mark (3AH for ":") of Intel Hex format. After receiving the start mark, the boot program receives a range of data from record length to checksum and writes the received data to the specified RAM addresses successively. If a receive error or checksum error occurs, the boot program stops operation without sending error code to the PC. The boot program executes the SUM calculation routine upon detecting the end record. Thus, after sending the end record, the PC should be placed in a state in which it waits for SUM data. 8. 9. 10. The (n-3)th and (n-2)th bytes are used to send the SUM value to the PC in the order of upper byte and lower byte. For details on how to calculate SUM, see "SUM calculation" to be described later. SUM calculation is performed after detecting the end record only when no receives error or checksum error has occurred. Immediately after SUM calculation is completed, the boot program sends the SUM value to the PC. After sending the end record, the PC should determine whether or not writing to RAM has completed successfully based on whether or not the SUM value is received from the boot program. 11. After sending the SUM value, the boot program waits for the user program start command (C0H). If the SUM value is correct, the PC should send the user program start command in the (n-1)th byte. 12. The n'th byte is used to echo back the user program start command to the PC. After sending the echo back data, the boot program sets the stack pointer to 4A000H and jumps to the address that is received first as Intel Hex format data. 13. If the user program start command is not correct or a receive error has occurred, the boot program stops operation after sending the error code to the PC three times. 92CF26A-53 2007-11-21 TMP92CF26A b) Error codes The boot program uses the error codes shown in Table 3.4.12 to notify the PC of its processing status. Table 3.4.12 Error Codes Error Code 62H 64H A1H A3H Unsupported baud rate Invalid operation command Framing error in received data Overrun error in received data Meaning Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC. Note 2: After sending an error code, the boot program stops operation. c) SUM calculation 1. Calculation method SUM is calculated by adding data in bytes and is returned in words, as explained below. Example: If the data to be calculated consists of the 4 bytes shown to the left, SUM is calculated as follows: A1H + B2H + C3H + D4H = 02EAH SUM (HIGH) = 02H SUM (LOW) = EAH A1H B2H C3H D4H 2. Data to be calculated SUM is calculated from the data at the first received address through the last received address. Even if received addresses are not continuous, unwritten addresses are also included in SUM calculation. The user program should not contain unwritten gaps. 92CF26A-54 2007-11-21 TMP92CF26A d) Notes on Intel Hex format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for ":") of the next record. If data other than 3AH is received between records, it is ignored. Once the PC program has finished sending the checksum of an end record, it must wait for 2 bytes of data (upper and lower bytes of SUM) before sending any other data. This is because after receiving the checksum of an end record, the boot program calculates SUM and returns the result to the PC in 2 bytes. Writing to areas other than internal RAM may cause incorrect operation. To transfer a record, set the paragraph address to 0000H. Since the address pointer is initially set to 00H, the record type to be transferred first does not have to be an address record. Addresses 3000H to 21FFFH are allocated as the user program download area. A user program in Intel Hex format (ASCII codes) must be converted into binary data in advance, as explained in the example below. Example: How to convert an Intel Hex file into binary format The following shows how an Intel Hex format file is displayed on a text editor. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF However, the actual data consists of ASCII codes, as shown below. 3A3130333030303030303630374631303030333030303046323031303330303030 423146313630313042370D0A3A303030303030303146460D0A Thus, the ASCII codes must be converted into binary data based on the conversion rules shown in the table below. 2. 3. 4. 5. 6. ASCII Code 3A 30 to 39 41 or 61 42 or 62 43 or 63 44 or 64 45 or 65 46 or 66 0D0A Intel Hex format Data record Binary Data 3A (Only 3A remains the same.) 0 to 9 A B C D E F Delete 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Record type Address Record length Checksum End record : (Start mark) 3A 00 0000 01 FF Data Record type Address Record length : (Start mark) 92CF26A-55 2007-11-21 TMP92CF26A e) User program receive error If either of the following error conditions occurs while a user program is being received, the boot program stops operation. If the record type is other than 00H, 01H, or 02H If a checksum error occurs f) Measured frequency/baud rate error When the boot program receives matching data, it measures the oscillation frequency. If an error is within plus or minus 3%, the boot program decides on that frequency. Each baud rate includes a setting error as shown in Table 3.4.13. For example, in the case of 10.00 MHz /9600 bps, the baud rate is actually set at 9615.38 bps. To establish communication, the sum of the baud rate setting error and the measured frequency error must be within plus or minus 3 %. Table 3.4.13 Baud Rate Setting Errors (%) 9600 bps 19200 bps 0.2 0.2 -0.7 0.2 38400 bps - - - -1.4 57600 bps - - - - 115200 bps - - - - -: Not supported 6.000 MHz 8.000 MHz 9.000 MHz 10.000 MHz 0.2 0.2 0.2 0.2 92CF26A-56 2007-11-21 TMP92CF26A (5) Others a) Handshake function Although the CTS pin is available in the TMP92CF26A, the boot program does not use it for transfer control. b) RS-232C connector The RS-232C connector must not be connected or disconnected while the boot program is running. c) Software on the PC When downloading a user program via UART, special application software is needed on the PC. 92CF26A-57 2007-11-21 TMP92CF26A 3.4.5 Downloading a User Program via USB (1) Connection example Figure 3.4.5 shows an example of connections for downloading a user program via USB (using a 16-bit NOR Flash memory device as program memory). PUCTL R4 = 100 k R2 = 27 R3 = 27 PU6, LD22 RXD,P91 P82, CS2 P70, RD PJ2, SRWR CE OE WE R1 = 1.5 k PC D+ D- AM0 AM1 TMP92CF26A D0 to D15 NOR Flash D0 to D15 A1 to A20 A0 to A19 Note 1: The value of pull-up and pull-down resistors are recommended values. Note 2: The PU6 and LD22 pins are assigned as PUCTL (pull-up control) output for USB. Be careful about this if the system uses the 24-bit TFT display function. Note 3: Since the input gates of the D+ and D- pins are always open even at unused (unaccessed) times, these pins must be set to a fixed level to prevent flow-through current. Although the level setting is not specified in the above diagram, be sure to fix the level of the D+ and D- pins by referring to the chapter on USB. Figure 3.4.5 USB Connection Example (2) USB interface specifications When a user program is downloaded via USB, the oscillation frequency should be set to 10.00 MHz. The transfer speed should be fixed to full speed (12 Mbps). The boot program uses the following two transfer types. Table 3.4.14 Transfer Types Used by the Boot Program Transfer Type Control Transfer Bulk Transfer Description Used for transmitting standard requests and vendor requests. Used for responding to vendor requests and transmitting a user program. 92CF26A-58 2007-11-21 TMP92CF26A The following shows an overview of the USB communication flow. (Legends) Control Transfer Bulk Transfer Host (PC) Connection Recognition Send GET_DISCRIPTOR TMP92CF26A Send DESCRIPTOR information Send the microcontroller information command Prepare microcontroller information data Send microcontroller information data Check data Data Transfer Convert Intel Hex format data into binary data Send the microcontroller information command Prepare microcontroller information data Send microcontroller information data Check data Send the user program transfer start command Load the received data into the specified RAM address area & prepare microcontroller information data (If the received data cannot be loaded into RAM for some reason, it is discarded.) Transfer End Processing Transmit the transfer result command 2 seconds after completion of user program transfer Check data Send the transfer result command Send data Send a user program Send transfer result data Prepare transfer result data Branch to internal RAM Figure 3.4.6 Overall Flowchart 92CF26A-59 2007-11-21 TMP92CF26A Table 3.4.15 Vendor Request Commands Command Name Microcontroller information command User program transfer start command Value of bRequest 00H Operation Notes Send microcontroller Microcontroller information data is information sent by bulk IN transfer after the setup stage is completed. Receive a user program Set the size of a user program in wIndex. The user program is received by bulk OUT transfer after the setup stage is completed. 02H User program transfer result command 04H Send the transfer result Transfer result data is sent by bulk IN transfer after the setup stage is completed. Table 3.4.16 Setup Command Data Structure Field Name bmRequestType 40H Value D7 D6-D5 D4-D0 2: Vendor 0: Device Meaning 0: Host to Device bRequest 00H, 02H, 04H 00H: Microcontroller information 02H: User program transfer start 04H: User program transfer result wValue wIndex wLength 00H~FFFFH 00H~FFFFH 0000H Own data number (Not used by boot program) User program size (Used when starting a user program transfer) Fixed 92CF26A-60 2007-11-21 TMP92CF26A Table 3.4.17 Standard Request Commands Standard Request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR SET_DISCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME Response Method Automatic response by hardware Automatic response by hardware Automatic response by hardware Automatic response by hardware Automatic response by hardware Not supported Automatic response by hardware Automatic response by hardware Automatic response by hardware Automatic response by hardware Ignored Table 3.4.18 Information Returned by GET_DISCRIPTOR DeviceDescriptor Field Name Blength BdescriptorType BcdUSB BdeviceClass BdeviceSubClass BdeviceProtocol BmaxPacketSize0 IdVendor IdProduct BcdDevice Imanufacturer Iproduct IserialNumber BnumConfigurations 12H 01H 0110H 00H 00H 00H 40H 0930H 6504H 0001H 00H 00H 00H 01H Value 18 bytes Device descriptor USB Version 1.1 Meaning Device class (Not in use) Sub command (Not in use) Protocol (Not in use) EP0 maximum packet size (64 bytes) Vendor ID Product ID (0) Device version (v0.1) Index value of string descriptor indicating manufacturer name Index value of string descriptor indicating product name Index value of string descriptor indicating product serial number There is one configuration. 92CF26A-61 2007-11-21 TMP92CF26A ConfigrationDescriptor Field Name bLength bDescriptorType wTotalLength 09H 02H 0020H Value 9 bytes Meaning Configuration descriptor Total length (32 bytes) which each descriptor of both configuration descriptor, interface and endpoint is added. There is one interface. Configuration number 1 Index value of string descriptor indicating configuration name (Not in use) Bus power Maximum power consumption (49 mA) bNumInterfaces bConfigurationValue iConfiguration bmAttributes MaxPower 01H 01H 00H 80H 31H InterfaceDescriptor Field Name bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iIinterface 09H 04H 00H 00H 02H FFH 00H 50H 00H Bulk only protocol Index value of string descriptor indicating interface name (Not in use) Value 9 bytes Interface descriptor Interface number 0 Meaning Alternate setting number 0 There are two endpoints. Specified device EndpointDescriptor Field Name Value Meaning 92CF26A-62 2007-11-21 TMP92CF26A Table 3.4.19 Information Returned for the Microcontroller Information Command Microcontroller Information TMP92CZ26 ASCII Code 54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H Note: TMP92CF26AXBG share ROM code with TMP92CZ26AXBG. Please be careful. Table 3.4.20 Information Returned for the User Program Transfer Result Command Transfer Result No error User program not received Received file not in Intel Hex format User program size error Download address error Protocol error or other error Value 00H 02H 04H 06H 08H 0AH Error Conditions The user program transfer result is received without the user program transfer start command being received first. The first data of a user program is not ":" (3AH). The size of a received user program is larger than the value set in wIndex of the user program transfer start command. The specified user program download address is not in the designated area. The user program transfer start or user program transfer result command is received first. A checksum error is detected in the Intel Hex file. A record type error is detected in the Intel Hex file. The length of an address record in the Intel Hex file is 3 or longer. The length of an end record in the Intel Hex file is other than 0. 92CF26A-63 2007-11-21 TMP92CF26A (3) Description of the USB boot program operation The boot program loads a user program in Intel Hex format sent from the PC into the internal RAM. When the user program has been loaded successfully, the user program starts executing from the first address received. The boot program thus enables users to perform customized on-board programming. a. Operation procedure 1. 2. 3. 4. Connect the USB cable. Set the AM0 and AM1 pins to "1" and reset the microcontroller. After recognizing USB connection, the PC checks the information on the connected device using the GET_DISCRIPTOR command. The PC sends the microcontroller information command by control transfer (vendor request). After the setup stage is completed, the PC checks microcontroller information data by bulk IN transfer. Upon receiving the microcontroller information command, the boot program prepares microcontroller information in ASCII code. The PC prepares the user program to be loaded by converting an Intel Hex file into binary format. The PC sends the user program transfer start command by control transfer (vendor request). After the setup stage is completed, the PC transfers the user program by bulk OUT transfer. After the user program has been transferred, the PC waits for about two seconds and then sends the user program transfer result command by control transfer (vendor request). After the setup stage is completed, the PC checks the transfer result by bulk IN transfer. Upon receiving the user program transfer result command, the boot program prepares the transfer result value to be returned. 5. 6. 7. 8. 9. 10. If the transfer result is other than OK, the boot program enters the error processing routine and will not automatically recover from it. In this case, terminate the device driver on the PC and retry from step 2. 92CF26A-64 2007-11-21 TMP92CF26A b. Notes on the user program format (binary) 1. After receiving the checksum of a record, the boot program waits for the start mark (3AH for ":") of the next record. If data other than 3AH is received between records, it is ignored. Since the address pointer is initially set to 00H, the record type to be transferred first does not have to be an address record. Addresses 3000H to 21FFFH (124 Kbytes) are allocated as the user program download area. The user program should be contained within this area. 2. 3. Note: In USB transfer, the size of program is set by wIndex from addresses 0000H to FFFFH. Therefore, the transferred Object size becomes 64K byte max. Please be careful. 4. A user program in Intel Hex format (normally written in ASCII code) must be converted into binary data before it can be transferred. See the example below for how to convert an Intel Hex file into binary format. When a user program is downloaded via USB, the maximum allowed record length is 250 bytes. Example: Transfer data when writing 16-byte data in Intel Hex format from address 3000H The following shows how an Intel Hex format file is displayed on a text editor. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF However, the actual data consists of ASCII codes, as shown below. 3A3130333030303030303630374631303030333030303046323031303330303030 423146313630313042370D0A3A303030303030303146460D0A Thus, the ASCII codes must be converted into binary data based on the conversion rules shown in the table below. ASCII Code 3A 30~39 41 or 61 42 or 62 43 or 63 44 or 64 45 or 65 46 or 66 0D0A Binary Data 3A (Only 3A remains the same.) 0~9 A B C D E F Delete The above Intel Hex file is converted into binary data as follows: Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Record type Address Record length : (Start mark\) End record 3A 00 0000 01 FF Checksum Record type Address Record length : (Start mark) Checksum 92CF26A-65 2007-11-21 TMP92CF26A (4) Others a) USB connector The USB connector must not be connected or disconnected while the boot program is running. b) Software on the PC To download a user program via USB, a USB device driver and special application software are needed on the PC. 92CF26A-66 2007-11-21 TMP92CF26A 3.5 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register External interrupts: 9 sources * Interrupts on external pins (INT0 to INT7, INTKEY) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU interrupt mask register 92CF26A-67 2007-11-21 TMP92CF26A Interrupt processing DMA soft start request Interrupt specified by DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue "V" read interrupt request F/F clear Start specified by HDMA YES to HDMA processing flow General-purpose interrupt processing PUSH PC PUSH SR SR NO Data transfer by micro DMA Micro DMA processing COUNT COUNT - 1 PC (FFFF00H + V) COUNT = 0 Interrupt processing program NO YES Clear vector register generating micro DMA transfer end interrupt (INTTC0) RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.5.1 Interrupt processing Sequence 92CF26A-68 2007-11-21 TMP92CF26A 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: The smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). (3) The CPU sets the value of the CPU's interrupt mask register 92CF26A-69 2007-11-21 TMP92CF26A Table 3.5.1 TMP92CF26A Interrupt Vectors and Micro DMA/HDMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Maskable Non maskable Type Interrupt Source and Source of Micro DMA Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction (Reserved) INTWD: Watchdog timer Micro DMA (Note 2) INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input (TSI) INTALM: ALM(8KHz, 512Hz, 64Hz, 2Hz, 1Hz) INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTA6: 8-bit timer 6 INTTA7: 8-bit timer 7 INTP0: Protect 0 (Write to SFR) (Reserved) INTTA0: 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 0 INTKEY: Key wakeup INTRTC: RTC (Alarm interrupt) (Reserved) INTLCD: LCDC INTRX: Serial receive end INTTX: Serial transmission end INTTB10: 16-bit timer 1 INTTB11: 16-bit timer 1 INT5: INT5 pin input INT6: INT6 pin input INT7: INT7 pin input INTI2S0: I2S (Channel 0) INTI2S1: I2S (Channel 1) INTADM: AD Monitor function INTSBI: SBI INTSPIRX: SPIC receive INTSPITX: SPIC transmission INTRSC: NAND Flash controller INTRDY: NAND Flash controller INTUSB: USB (Reserved) (Reserved) Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Micro DMA Address Refer /HDMA Start to Vector Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H - 0AH(Note 1) 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note 1) 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 92CF26A-70 2007-11-21 TMP92CF26A Default Priority 51 52 53 54 55 56 57 58 59 60 - to - Type Interrupt Source and Source of Micro DMA Request INTADHP: AD most priority conversion end INTAD: AD conversion end INTTC0/INTDMA0: Micro DMA0 /HDMA0 end INTTC1/INTDMA1: Micro DMA1 /HDMA1 end INTTC2/INTDMA2: Micro DMA2 /HDMA2 end INTTC3/INTDMA3: Micro DMA3 /HDMA3 end Vector Value 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH Micro DMA Address Refer /HDMA Start to Vector Vector FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH - to - Maskable INTTC4/INTDMA4: Micro DMA4 /HDMA4 end INTTC5/INTDMA5: Micro DMA5 /HDMA5 end INTTC6 INTTC7 (Reserved) : Micro DMA6 end : Micro DMA7 end Note 1: When initiating micro DMA/HDMA , set at edge detect mode. Note 2 : Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupt. 92CF26A-71 2007-11-21 TMP92CF26A 3.5.1 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CF26A also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.23 DMA controller. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented through the CPU, when the CPU is placed in a stand-by state (IDLE2, IDLE1, STOP) by a HALT instruction, the requirement of the micro DMA will be ignored (Pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. Note: When using the micro DMA transfer end interrupt, always write "1" to bit 7 of SIMC register. (1) Micro DMA operation When an interrupt request is generated by an interrupt source that specified by the micro DMA /HDMA start vector register, and Micro DMA start is specified by DMA selection register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. When IFF = 7, Micro DMA request cannot be accepted. The 8 micro DMA channels allow micro DMA processing to be set for up to 8 types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by "1". If the value of the counter after it has been decremented is not "0", DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is "0", a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA /HDMA start vector register is cleared to "0", the next micro DMA operation is disabled and micro DMA processing terminates. If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA /HDMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA /HDMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e, interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. 92CF26A-72 2007-11-21 TMP92CF26A If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest). Note: Don't start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that channel number is biggest (priority is lowest) is not started.(Because interrupt flag is cleared by micro DMA that priority is highest) Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: 1byte transfer, 2byte (One word) transfers and 4byte transfers. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.5.2 (4) "Detailed description of the transfer mode register". Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 48 different interrupts - the 47 interrupts shown in the micro DMA start vectors in Table 3.5.1 and a micro DMA soft start. Figure 3.5.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer Destination Address INC Mode (micro DMA transfers are the same in every mode except Counter Mode). (The conditions for this cycle are as follows: both source and destination memory are internal-RAM and multiple of 4 numbered source and destination addresses). 1 state (1) fSYS A23 to A0 (2) (3) (4) (5) src dst Note: In fact, src and dst address are not outputted to A23-A0 pins because they are internal RAM address. Figure 3.5.2 Timing for micro DMA cycle States (1) and (2): Instruction fetch cycle (Prefetches the next instruction code) State (3): Micro DMA read cycle. State (4): Micro DMA writes cycle. State (5): (The same as in state (1), (2).) 92CF26A-73 2007-11-21 TMP92CF26A (2) Soft start function The TMP92CF26A can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the register DMAR. Writing "1" to each bit of DMAR register causes micro DMA or HDMA to be performed once. On completion of the transfer, the bits of DMAR for the completed channel are automatically cleared to "0". When writing again "1" to it, soft start can execute continuously until the DMA transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) become "0". When a burst is specified by the register DMAB, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is "0". Note1: If it is started by software, don't set any channels to start in same time. Note2: If be started sequentially, restart it after confirming micro DMA of all channels is completed (all micro DMA are set to "0"). Symbol Name DMA Request Address 109H (Prohibit RMW) 7 DREQ7 6 DREQ6 0 5 DREQ5 0 4 DREQ4 0 R/W 3 DREQ3 0 1: Start DMA 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR 0 (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr,r can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Micro DMA source address register 0 Micro DMA destination address register 0 Micro DMA counter register 0 Micro DMA mode register 0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits Micro DMA source address register 7 Micro DMA destination address register 7 Micro DMA counter register 7 Micro DMA mode register 7 92CF26A-74 2007-11-21 TMP92CF26A (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAMn[4:0] 000zz Destination INC mode (DMADn +) (DMASn) DMACn 001zz Mode Description Execution Time DMACn - 1 5 states if DMACn = 0 then INTTCn Destination DEC mode (DMADn -) (DMASn) DMACn 010zz DMACn - 1 if DMACn = 0 then INTTCn Source INC mode (DMADn) DMACn 011zz (DMASn +) DMACn - 1 5 states 5 states if DMACn = 0 then INTTCn Source DEC mode (DMADn) DMACn 100zz (DMASn -) DMACn - 1 5 states if DMACn = 0 then INTTCn Source and destination INC mode (DMADn +) (DMASn +) DMACn 101zz DMACn - 1 If DMACn = 0 then INTTCn Source and destination DEC mode (DMADn -) (DMASn -) DMACn 110zz DMACn - 1 If DMACn = 0 then INTTCn Destination and fixed mode (DMADn) (DMASn) DMACn 1 1 1 00 DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMACn DMASn + 1 DMACn - 1 5 states 5 states 6 states 6 states If DMACn = 0 then INTTCn ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = Reserved Note 1: n stands for the micro DMA channel number (0 to 7). DMADn+/DMASn+: Post increment (Register value is incremented after transfer). DMADn-/DMASn-: Post decrement (Register value is decremented after transfer). "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note 2: The transfer mode register should not be set to any value other than those listed above. Note 3: The execution state number shows number of best case (1-state memory access). 92CF26A-75 2007-11-21 TMP92CF26A 3.5.2 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 59 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to "0" in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when the CPU receives a HDMA request (when HDMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0 or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt's vector address to the CPU. The CPU compares the mask value set in 92CF26A-76 2007-11-21 Interrupt controller Interrupt request F/F Q Interrupt mask F/F RESET Priority encorderInterrupt request signal to CPU CPU 1 INTWD S RESET R Interrupt vector read V = 20H V = 24H Priority setting register IFF2 to 0 3 3 INTRQ2 to 0 3 Interrupt mask detect A B Decorder 1 7 6 6 Dn EI 1 to 7 DI Interrupt request signal During IDLE1 During STOP Dn + 1 Dn + 2 C D Q CLR Interrupt request F/F Q Interrupt request F/F 52 Interrupt vector generator Y1 Y2 Y3 Y4 Y5 Y6 INT0 Dn + 3 D0 D1 Reset S R Interrupt vector read Micro DMA acknowledge 1 2 Highest A priority 3 interrupt B C 4 level select 5 6 7 INTRQ20 IFF 20 then 1. INT1 INT2 INT3 INT4 INTALM INTTA4 INTTA5 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H D2 D3 D4 D5 D6 D7 RESET Figure 3.5.3 Block Diagram of Interrupt Controller 92CF26A-77 Interrupt vector read 8 input OR 8 V = E0H V = E4H V = E8H V = ECH HALT release Micro DMA/HDMA counter 0 interrupt INTTC4/INTDMA4 INTTC5/INTDMA5 INTTC6 INTTC7 INT0,1 to 4,INTKEY, INTRTC INTALM Micro DMA request Micro DMA/HDMA start vector setting register IFF7 then 0 Soft start 0 1 2 7 3 3 51 S Selector D5 D4 D3 D2 D1 D0 D Q CLR 6 INTTC0/ INTDMA0 A B C Micro DMA channel priority encorder 6 input OR 6 Micro DMA channel specification HDMA RESET HDMA request DMA0V DMA1V DMA2V DMA3V DMA4V DMA5V DMA6V DMA7V 0 1 2 5 A B C 6 HDMA channel priority encorder 3 3 HDMA channel TMP92CF26A 2007-11-21 Micro DMA/HDMA selection register TMP92CF26A (1) Interrupt priority setting registers Name INT0 enable Symbol Address 7 - - 6 - - 5 - - 4 - 3 I0C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 INT7 I7M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 0 ITA6M2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 I7M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 ITA6M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 I7M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 0 ITA6M0 0 INTE0 F0H Always write "0". INT2 INTE12 INT1 & INT2 enable D0H I2C R 0 INT3 & INT4 enable I4C R 0 INT5 & INT6 enable I6C R 0 INT7 enable - - 0 - INTE7 D3H - - - Always write "0". INTTA1 (TMRA1) INTETA01 INTTA0 & INTTA1 enable D4H ITA1C R 0 INTTA2 & INTTA3 enable ITA3C R 0 INTTA4 & INTTA5 enable ITA5C R 0 INTTA6 & INTTA7 enable ITA7C R 0 0 0 ITA7M2 0 ITA5M2 0 ITA3M2 ITA1M2 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 ITA7M1 R/W 0 0 0 ITA7M0 INTTA7 (TMRA7) INTETA67 D7H 0 ITA5M0 INTTA5 (TMRA5) INTETA45 D6H 0 ITA3M0 INTTA3 (TMRA3) INTETA23 D5H ITA1M0 - 0 INT6 INTE56 D2H I6M2 I6M1 R/W 0 0 I6M0 0 INT4 INTE34 D1H I4M2 I4M1 R/W 0 0 I4M0 I2M2 I2M1 R/W 0 0 I2M0 I1C R 0 I3C R 0 I5C R 0 I7C R 0 ITA0C R 0 ITA2C R 0 ITA4C R 0 ITA6C R 0 INTTA0 (TMRA0) INTTA2 (TMRA2) INTTA4 (TMRA4) INTTA6 (TMRA6) lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 92CF26A-78 2007-11-21 TMP92CF26A Symbol Name INTTB00 & Address 7 ITB01C R 0 6 ITB01M2 0 ITB11M2 0 INTTX0 ITX0M2 0 INTADM IADMM2 0 ISPITM2 0 - - 5 ITB01M1 R/W 0 ITB11M1 R/W 0 ITX0M1 R/W 0 IADMM1 R/W 0 4 ITB01M0 0 ITB11M0 0 ITX0M0 0 IADMM0 0 ISPITM0 0 - 3 ITB00C R 0 ITB10C R 0 IRX0C R 0 ISBI0C R 0 ISPIRC R 0 IUSBC R 0 2 1 0 ITB00M0 0 ITB10M0 0 IRX0M0 0 ISBIM0 0 ISPIRM0 0 IUSBM0 0 IALMM0 0 IRM0 0 IKM0 0 INTTB01 (TMRB0) D8H INTTB00 (TMRB0) ITB00M2 ITB00M1 R/W 0 0 INTTB10 (TMRB1) ITB10M2 ITB10M1 R/W 0 INTRX0 IRX0M2 0 INTSBI ISBIM2 0 ISPIRM2 0 INTUSB IUSBM2 0 INTALM IALMM2 0 INTRTC IRM2 0 INTKEY IKM2 0 ISBIM1 R/W 0 INTSPIRX ISPIRM1 R/W 0 IUSBM1 R/W 0 IALMM1 R/W 0 IRM1 R/W 0 IKM1 R/W 0 IRX0M1 R/W 0 0 INTETB0 INTTB01 enable INTTB10 & INTETB1 INTTB11 enable D9H INTTB11 (TMRB1) ITB11C R 0 INTRX0 & INTES0 INTTX0 enable DBH ITX0C R 0 INTSBI & INTESBIADM INTADM enable E0H IADM0C R 0 INTSPITX INTESPI INTSPI enable E1H ISPITC R 0 INTUSB enable - - - INTEALM INTALM enable E5H - - - INTERTC INTRTC enable E8H - - - INTEKEY INTKEY enable E9H - - - - - Always write "0". - IKC R 0 - - - Always write "0". - IRC R 0 - - - Always write "0". - IALMC R 0 ISPITM1 R/W 0 - - Always write "0". INTEUSB E3H lxxM2 0 0 0 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 0 1 1 1 1 92CF26A-79 2007-11-21 TMP92CF26A Symbol Name INTLCD enable Address 7 - - 6 - - 5 - - 4 - 3 ILCD1C R 0 2 INTLCD ILCDM2 0 INTI2S0 II2S0M2 0 INTRDY IRDYM2 0 INTP0 IP0M2 0 INTAD IADM2 0 1 ILCDM1 R/W 0 II2S0M1 R/W 0 IRDYM1 R/W 0 IP0M1 R/W 0 IADM1 R/W 0 0 ILCDM0 0 II2S0M0 0 IRDYM0 0 IP0M0 INTELCD EAH Always write "0". INTI2S0 & INTEI2S01 INTI2S1 enable EBH INTI2S1 II2S1C R 0 INTRSC & INTENDFC INTRDY enable ECH IRSCC R 0 INTP0 enable - - 0 - INTEP0 EEH - - - Always write "0". INTAD & 0INTEAD INTADHP enable EFH INTADHP IADHPC IADHPM2 IADHPM1 IADHPM0 R 0 0 R/W 0 0 - 0 INTRSC IRSCM2 IRSCM1 R/W 0 0 IRSCM0 II2S1M2 II2S1M1 R/W 0 0 II2S1M0 I I2S0C R/W 0 IRDYC R 0 IP0C R 0 IADC R/W 0 IADM0 0 lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 92CF26A-80 2007-11-21 TMP92CF26A Symbol Name INTTC0/INTDMA0 & INTTC1/INTDMA1 enable Address 7 ITC1C 6 ITC1M2 5 ITC1M1 R/W 4 ITC1M0 3 ITC0C R 2 ITC0M2 1 ITC0M1 R/W 0 ITC0M0 INTTC1/INTDMA1 INTETC01 /INTEDMA01 F1H INTTC0/INTDMA0 /IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0 R 0 0 ITC3M2 0 ITC3M1 R/W 0 ITC5M2 0 ITC5M1 R/W 0 ITC7M2 0 - - 0 ITC7M1 R/W 0 - - Always write "0". 0 - 0 ITC7M0 INTTC7 (DMA7) 0 ITC5M0 INTTC5/INTDMA5 0 ITC3M0 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 ITCWD R 0 - - - 0 INTWD - - - 0 ITC6M2 0 ITC4M2 0 ITC2M2 0 ITC2M1 R/W 0 ITC4M1 R/W 0 ITC6M1 R/W 0 0 0 ITC6M0 INTTC6 (DMA6) 0 ITC4M0 INTTC4/INTDMA4 0 ITC2M0 INTTC3/INTDMA3 INTETC23 /INTEDMA23 INTTC2/INTDMA2 & INTTC3/INTDMA3 enable F2H ITC3C R 0 INTTC4/INTDMA4 & INTTC5/INTDMA5 enable F3H ITC5C R 0 INTTC6 & INTTC7 enable ITC7C R 0 INTWD enable - - INTTC2/INTDMA2 /IDMA3C /IDMA3M2 /IDMA3M1 /IDMA3M0 /IDMA2C /IDMA2M2 /IDMA2M1 /IDMA2M0 INTETC45 /INTEDMA45 /IDMA5C /IDMA5M2 /IDMA5M1 /IDMA5M0 /IDMA4C /IDMA4M2 /IDMA4M1 /IDMA4M0 INTETC67 F4H INTWDT F7H lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 92CF26A-81 2007-11-21 TMP92CF26A (1) External interrupt control Symbol Name Address 7 I5EDGE 0 0: Rising 1: Falling 6 I4EDGE 0 0: Rising 1: Falling 5 I3EDGE W 0 0: Rising 1: Falling 4 I2EDGE 0 0: Rising 1: Falling 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE R/W 0 0:Edge mode 1: Level mode I7EDGE 0 - 0 Always write "0". Interrupt IIMC0 input mode control 0 F6H (Prohibit RMW) INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 I6EDGE W 0 0: Rising 1: Falling Interrupt IIMC1 input mode control 0 FAH (Prohibit RMW) 0 0: Rising 1: Falling INT7EDGE INT6EDGE Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. (change (IIMC0), XXXXXX0-B (INTCLR), 0AH ; Switches from level to edge. ; Clears interrupt request flag. ; Wait EI execution NOP NOP NOP EI X: Don't care, -: No change Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. Note 3: In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and INT7 don't depend on IIMC1 register setting. INT6 and INT7 operate by setting TBnMOD Settings of External Interrupt Pin Function Interrupt INT0 Pin Name PC0 Mode Rising edge Falling edge High level Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Setting Method INT1 INT2 INT3 INT4 INT5 INT6 INT7 PC1 PC2 PC3 P96 PP3 PP4 PP5 92CF26A-82 2007-11-21 TMP92CF26A (2) SIO receive interrupt control Symbol Name Address 7 - W SIO SIMC interrupt mode control 0 F5H (Prohibit RMW) Always write "0" (Note) 0 Always write "0" 6 - 5 4 3 2 1 0 IR0LE W 1 0:INTRX0 edge mode 1:INTRX0 level mode Note: When using the micro DMA transfer end interrupt, always write "1". INTRX0 edge enable 0 1 Edge detect INTRX0 "H" level INTRX0 92CF26A-83 2007-11-21 TMP92CF26A (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start vector, as given in Table 3.5.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH ; Clears interrupt request flag INT0. Symbol Name Interrupt clear control Address F8H (Prohibit RMW) 7 CLRV7 0 6 CLRV6 0 5 CLRV5 0 4 CLRV4 W 0 3 CLRV3 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR Interrupt vector (4) Micro DMA start vector registers These registers assign micro DMA /HDMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA /HDMA start vector value matches the vector set in one of these registers is designated as the micro DMA /HDMA start source. When the micro DMA transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) value reaches "0", the micro DMA /HDMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA /HDMA start vector register is cleared, and the micro DMA /HDMA start source for the channel is cleared. Therefore, in order for micro DMA /HDMA processing to continue, the micro DMA /HDMA start vector register must be set again during processing of the micro DMA /HDMA transfer end interrupt. If the same vector is set in the micro DMA /HDMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA /HDMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA /HDMA transfer is complete. If the micro DMA /HDMA start vector for this channel has not been set in the channel's micro DMA /HDMA start vector register again, micro DMA /HDMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA /HDMA chaining.) 92CF26A-84 2007-11-21 TMP92CF26A Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 DMA4V4 0 DMA5V4 0 DMA6V4 0 DMA7V4 0 3 DMA0V3 R/W 0 DMA1V3 R/W 0 DMA2V3 R/W 0 DMA3V3 R/W 0 DMA4V3 R/W 0 DMA5V3 R/W 0 DMA6V3 R/W 0 DMA7V3 R/W 0 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 DMA4V2 0 DMA5V2 0 DMA6V2 0 DMA7V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA4V1 0 DMA5V1 0 DMA6V1 0 DMA7V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA4V0 0 DMA5V0 0 DMA6V0 0 DMA7V0 0 DMA0V start vector 100H 0 DMA1V5 DMA0 start vector DMA1 DMA1V start vector 101H 0 DMA2V5 DMA1 start vector DMA2 DMA2V start vector 102H 0 DMA3V5 DMA2 start vector DMA3 DMA3V start vector 103H 0 DMA4V5 DMA3 start vector DMA4 DMA4V start vector 104H 0 DMA5V5 DMA5 DMA5V start vector 105H 0 DMA6V5 DMA6 DMA6V start vector 106H 0 DMA7V5 DMA7 DMA7V start vector 107H 0 DMA4 start vector DMA5 start vector DMA6 start vector DMA7 start vector (5) Micro DMA/HDMA select register This register selectable that is started either Micro DMA or HDMA processing. Micro DMA /HDMA start vector register (DMAnV) shared with both functions. When interrupt which match with vector value that is set to DMA/HDMA start vector register generated, use this register. Symbol NAME Micro DMASEL DMA/ HDMA select 10AH 0 0:Micro DMA5 0 0:Micro DMA4 0 0:Micro DMA3 1:HDMA3 Address 7 6 5 4 3 R/W 2 1 0 DMASEL5 DMASEL4 DMASEL3 DMASEL2 DMASEL1 DMASEL0 0 0:Micro DMA2 1:HDMA2 0 0:Micro DMA1 1:HDMA1 0 0:Micro DMA0 1:HDMA0 1:HDMA5 1:HDMA4 92CF26A-85 2007-11-21 TMP92CF26A (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches "0". Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to "1" specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address 7 DBST7 DMAB DMA burst 108H 0 6 DBST6 0 5 DBST5 0 4 DBST4 R/W 0 3 DBST3 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 1: DMA request on Burst mode 92CF26A-86 2007-11-21 TMP92CF26A (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., "NOP" x 3 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) INT0 level mode When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC0), 00H LD (INTCLR), 0AH NOP NOP NOP EI In level mode (The register SIMC 92CF26A-87 2007-11-21 TMP92CF26A 3.6 DMAC (DMA Controller) The TMP92CF26A incorporates a DMA controller (DMAC) having six channels. This DMAC can realize data transfer faster than the micro DMA function by the 900/H1 CPU. The DMAC has the following features: 1) Six independent channels of DMA 2) Two types of transfer start requests Hardware request (using an interrupt source connected with the INTC) or software request can be selected for each channel. 3) Various source/destination combinations The combination of transfer source and destination can be selected for each channel from the following four types: memory to memory, memory to I/O, I/O to memory, I/O to I/O. 4) Transfer address mode Only the dual address mode is supported. 5) Dual-count mechanism and DMA end interrupt Two count registers are provided to execute multiple DMA transfers by one DMA request and to generate multiple DMA requests at a time. The DMA end interrupt (INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine can be used to prepare for the next processing. 6) Priorities among DMA channels (the same as the micro DMA acceptance specifications of the INTC) DMA requests are basically accepted in the order in which they are asserted. If more than one request is asserted simultaneously or it looks as if two requests were asserted simultaneously because one of the requests has been put on hold while other processing was being performed, the smaller-numbered channel is given a higher priority. 7) DMAC bus occupancy limiting function The DMAC incorporates a special timer for limiting its bus occupancy time to avoid excessive interference with the CPU or LCDC operation. 8) The DMAC can be used in HALT (IDLE2) mode. 92CF26A-88 2007-11-21 TMP92CF26A 3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. Bus Multiplexer Address Bus SDRAM Controller LCD Controller State Address Bus Data Bus State Address Bus Bus REQ Bus ACK Data Bus State Source Memory, I/O Bus ACK INTC (Interrupt Controller) Bus REQ CPU Interrupt REQ DMAnV 7 0 DMASn 31 DMAC or micro DMA request source setting DMAR DMAC or micro DMA soft start setting DMAB Micro DMA burst setting DMASEL DMAC or micro DMA select setting Bus REQ Micro DMA ACK, INTTCn Micro DMA REQ, Micro DMA Channel 0 Destination Memory, I/O Address Bus Address Bus Data Bus State Micro DMA source address setting DMADn Data Bus Micro DMA destination address setting State 15 0 DMACn Micro DMA transfer count setting 7 0 DMAMn Micro DMA mode setting DMA REQ, DMA Channel DMA ACK, INTDMAn DMAC HDMASn 31 DMA source address setting HDMADn Bus ACK 0 Address Bus State Data Bus DMA destination address setting 0 15 HDMACAn DMA transfer count A setting HDMACBn DMA transfer count B setting HDMAMn DMA mode setting HDMAE DMA operation enable/disable HDMATR DMA maximum bus occupancy time setting, mode setting 7 0 Note: "n" denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5). Figure 3.6.1 Overall Block Diagram 92CF26A-89 2007-11-21 TMP92CF26A 3.6.2 SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. When the source address is updated by DMA execution, HDMASn is also updated. HDMAS0 to HDMAS5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported. Therefore, specify an even-numbered address for transferring 2 bytes and an address that is an integral multiple of 4 for transferring 4 bytes. HDMASn Register 7 HDMASn bit Symbol Read/Write Reset State Function 0 0 0 0 DnSA7 6 DnSA6 5 DnSA5 4 DnSA4 R/W 3 DnSA3 0 2 DnSA2 0 1 DnSA1 0 0 DnSA0 0 Source address [7:0] for DMAn 15 bit Symbol Read/Write Reset State Function 0 DnSA15 14 DnSA14 0 13 DnSA13 0 12 DnSA12 0 R/W 11 DnSA11 0 10 DnSA10 0 9 DnSA9 0 8 DnSA8 0 Source address [15:8] for DMAn 23 bit Symbol Read/Write Reset State Function 0 DnSA23 22 DnSA22 0 21 DnSA21 0 20 DnSA20 0 R/W 19 DnSA19 0 18 DnSA18 0 17 DnSA17 0 16 DnSA16 0 Source address [23:16] for DMAn Source address [23:16] Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (0902H) (0912H) (0922H) (0932H) (0942H) (0952H) Source address [15:8] (0901H) (0911H) (0921H) (0931H) (0941H) (0951H) Source address [7:0] HDMAS0 (0900H) HDMAS1 (0910H) HDMAS2 (0920H) HDMAS3 (0930H) HDMAS4 (0940H) HDMAS5 (0950H) Note: Read-modify-write instructions can be used on all these registers. Figure3.6.2 HDMASn Register 92CF26A-90 2007-11-21 TMP92CF26A (2) HDMADn (DMA Transfer Destination Address Setting Register) The HDMADn register is used to set the DMA transfer destination address. When the destination address is updated by DMA execution, HDMADn is also updated. HDMAD0 to HDMAD5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported. Therefore, specify an even-numbered address for transferring 2 bytes and an address that is an integral multiple of 4 for transferring 4 bytes. HDMADn Register 7 HDMADn bit Symbol Read/Write Reset State Function 0 0 0 0 DnDA7 6 DnDA6 5 DnDA5 4 DnDA4 R/W 3 DnDA3 0 2 DnDA2 0 1 DnDA1 0 0 DnDA0 0 Destination address [7:0] for DMAn 15 bit Symbol Read/Write Reset State Function 0 DnDA15 14 DnDA14 0 13 DnDA13 0 12 DnDA12 R/W 0 11 DnDA11 0 10 DnDA10 0 9 DnDA9 0 8 DnDA8 0 Destination address [15:8] for DMAn 23 bit Symbol Read/Write Reset State Function 0 DnDA23 22 DnDA22 0 21 DnDA21 0 20 DnDA20 R/W 0 19 DnDA19 0 18 DnDA18 0 17 DnDA17 0 16 DnDA16 0 Destination address [23:16] for DMAn Destination address [23:16] Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (0906H) (0916H) (0926H) (0936H) (0946H) (0956H) Destination address [15:8] (0905H) (0915H) (0925H) Destination address [7:0] HDMAD0 (0904H) HDMAD1 (0914H) HDMAD2 (0924H) HDMAD3 (0934H) HDMAD4 (0944H) HDMAD5 (0954H) (0935H) (0945H) (0955H) Note: Read-modify-write instructions can be used on all these registers. Figure3.6.3 HDMADn Register 92CF26A-91 2007-11-21 TMP92CF26A (3) HDMACAn (DMA Transfer Count A Setting Register) The HDMACAn register is used to set the number of times a DMA transfer is to be performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even when the transfer count A is updated by DMA execution, HDMACAn is not updated. HDMACA0 to HDMACA5 have the same configuration. HDMACAn Register 7 HDMACAn bit Symbol Read/Write Reset State Function 0 0 0 0 DnCA7 6 DnCA6 5 DnCA5 4 DnCA4 R/W 3 DnCA3 0 2 DnCA2 0 1 DnCA1 0 0 DnCA0 0 Transfer count A [7:0] for DMAn 15 bit Symbol Read/Write Reset State Function 0 DnCA15 14 DnCA14 0 13 DnCA13 0 12 DnCA12 0 R/W 11 DnCA11 0 10 DnCA10 0 9 DnCA9 0 8 DnCA8 0 Transfer count A [15:8] for DMAn Transfer count A [15:8] Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (0909H) (0919H) (0929H) (0939H) (0949H) (0959H) Transfer count A [7:0] HDMACA0 (0908H) HDMACA1 (0918H) HDMACA2 (0928H) HDMACA3 (0938H) HDMACA4 (0948H) HDMACA5 (0958H) Note: Read-modify-write instructions can be used on all these registers. Figure3.6.4 HDMACAn Register 92CF26A-92 2007-11-21 TMP92CF26A (4) HDMACBn (DMA Transfer Count B Setting Register) The HDMACBn register is used to set the number of times a DMA request is to be made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request, FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated by DMA execution, HDMACBn is also updated. HDMACB0 to HDMACB5 have the same configuration. HDMACBn Register 7 HDMACBn bit Symbol Read/Write Reset State Function 0 0 0 0 DnCB7 6 DnCB6 5 DnCB5 4 DnCB4 R/W 3 DnCB3 0 2 DnCB2 0 1 DnCB1 0 0 DnCB0 0 Transfer count B [7:0] for DMAn 15 bit Symbol Read/Write Reset State Function 0 DnCB15 14 DnCB14 0 13 DnCB13 0 12 DnCB12 0 R/W 11 DnCB11 0 10 DnCB10 0 9 DnCB9 0 8 DnCB8 0 Transfer count B [15:8] for DMAn Transfer count B [15:8] Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (090BH) (091BH) (092BH) (093BH) (094BH) (095BH) Transfer count B [7:0] HDMACB0 (090AH) HDMACB1 (091AH) HDMACB2 (092AH) HDMACB3 (093AH) HDMACB4 (094AH) HDMACB5 (095AH) Note: Read-modify-write instructions can be used on all these registers. Figure3.6.5 HDMACBn Register 92CF26A-93 2007-11-21 TMP92CF26A (5) HDMAMn (DMA Transfer Mode Setting Register) The HDMAMn register is used to set the DMA transfer mode. HDMAM0 to HDMAM5 have the same configuration. HDMAMn Register 5 4 3 DnM4 0 DnM3 0 7 HDMAMn bit Symbol Read/Write Reset State Function 6 2 DnM2 R/W 0 1 DnM1 0 00: 1 byte 01: 2 bytes 10: 4 bytes 11: Reserved 0 DnM0 0 DMA transfer mode 000: Destination INC (I/O MEM) 001: Destination DEC (I/O MEM) 010: Source INC (MEM I/O) 011: Source DEC (MEM I/O) 100: Source/destination INC (MEM MEM) 101: Source/destination DEC (MEM MEM) 110: Source/destination fixed (I/O I/O) 111: Reserved (Note 2) Transfer data size Transfer mode [7:0] Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 HDMAM0 (090CH) HDMAM1 (091CH) HDMAM2 (092CH) HDMAM3 (093CH) HDMAM4 (094CH) HDMAM5 (095CH) Note 1: Read-modify-write instructions can be used on all these registers. Note 2: INC: Post-increment Dec: Post-decrement I/O: Fixed memory address MEM: Memory address to be incremented or decremented Figure3.6.6 HDMAMn Register 92CF26A-94 2007-11-21 TMP92CF26A (6) HDMAE (DMA Operation Enable Register) The HDMAE register is used to enable or disable the DMAC operation. Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to "0". HDMAE Register 7 HDMAE (097EH) bit Symbol Read/Write Reset State Function 0 0 0 0: Disable 1: Enable Note: Read-modify-write instructions can be used on this register. 6 5 DMAE5 4 DMAE4 3 DMAE3 R/W 2 DMAE2 0 1 DMAE1 0 0 DMAE0 0 DMA channel operation Figure3.6.7 HDMAE Register (7) HDMATR (DMA Maximum Bus Occupancy Time Setting Register) The HDMATR register is used to set the maximum duration of time the DMAC can occupy the bus. The TMP92CF26A does not have priority levels for bus arbitration. Therefore, once the DMAC owns the bus, other masters (such as the LCDC) must wait until the DMAC completes its transfer operation and releases the bus. This could lead to problems in the system. For example, if the LCDC cannot own the bus as required, the LCD display function may not work properly. To avoid such a situation, the DMAC limits the duration of its bus occupancy by using this timer register. When the DMAC occupies the bus for the duration of time set in this register, it releases the bus even if the specified DMA operation has not been completed yet. After waiting for 16 states, the DMAC asserts a bus request again to execute the rest of the DMA operation. The DMAC counts the bus occupancy time regardless of which channel is occupying the bus. To set the maximum bus occupancy time, ensure that the HDMAE register is set to "00H" and set HDMATR Note: In case of using S/W start with HDMA, transmission start is to set to "1" DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus occupation once with HDMATR function. HDMATR Register 7 HDMATR (097FH) bit Symbol Read/Write Reset State Function Timer operation 0: Disable 1: Enable 0 0 0 0 DMATE 6 DMATR6 5 DMATR5 4 DMATR4 R/W 3 DMATR3 0 2 DMATR2 0 1 DMATR1 0 0 DMATR0 0 Maximum bus occupancy time setting The value to be set in Note: Read-modify-write instructions can be used on this register. Figure3.6.8 HDMATR Register 92CF26A-95 2007-11-21 TMP92CF26A 3.6.3 DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is requested. Interrupt (DMA) request To general-purpose interrupt or micro DMA processing flow Interrupt specified by DMA start vector? No Yes Interrupt request F/F clear & bus REQ assert No Bus ACK? Yes Internal timer start HDMASn read HDMADn write Timer match? Yes No No HDMACAn -1=0? Yes Bus REQ deassert Yes HDMACBn -1=0? No INTDMAn assert END Figure 3.6.9 Overall Flowchart 92CF26A-96 2007-11-21 TMP92CF26A (2) Bus arbitration The TMP92CF26A includes three controllers (DMA controller, LCD controller, SDRAM controller) that function as bus masters apart from the CPU. These controllers operate independently and assert a bus request as required. The controller that receives a bus acknowledgement acts as the bus master. No priorities are assigned to these three controllers, and bus requests are processed in the order in which they are asserted. Once one of the controllers owns the bus, bus requests from other controllers are put on hold until the bus is released again. While one of the controllers is occupying the bus, CPU processing including non-maskable interrupt requests is also put on hold. (3) Transfer source and destination memory setting Either internal or external memory can be set as the source and destination memory or I/O to be accessed by the DMAC. Even when the MMU is used in external memory, the addresses to be accessed by the DMAC should be specified using logical addresses. The DMAC accesses the specified source and destination addresses according to the bus width and number of waits set in the memory controller and the bank settings made in the MMU. Although the bus sizing function is supported, the address alignment function is not supported. Therefore, specify an even-numbered address for transferring 2 bytes and an address that is an integral multiple of 4 for transferring 4 bytes. Table 3.6.1 Difference point of address setting between HDMA and micro DMA Data Length 1byte Source address 2byte 4byte 1byte Destination address 2byte 4byte HDMA No restriction Even address Address in multiples of 4 No restriction Even address Address in multiples of 4 Micro DMA No restriction (4) Operation timing The following diagram shows an example of operation timing for transferring 2 bytes from 16-bit memory connected with the CS2 area to 8-bit memory connected with the CS1 area. CPU execution cycle DMAC/read DMAC/write CPU execution cycle SDCLK int_xx busrq busak CS2 CS1 A23 A0 RD Undefined after interrupt request is asserted until DMAC read cycle is started 800000H 400000H 400001H SRWR SRLUB SRLLB D15 D0 1234H ZZ34H ZZ12H 92CF26A-97 2007-11-21 TMP92CF26A 3.6.4 Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I2S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be transferred to FIFO-RAM via I2S. Each time an INTI2S request is asserted, 64 bytes (4 bytes x 16 times) shall be transferred to FIFO-RAM using DMAC channel 0. Since INTI2S is an FIFO empty interrupt, the first data must be set in advance. Therefore, only the first 64 bytes shall be transferred by DMA soft start. After 32 Kbytes have been transferred, the INTDMA0 interrupt routine shall be activated to prepare for the next processing. (a) Main routine No 1 2 3 4 5 6 7 8 9 10 11 12 13 ldl ldl ldw ldw ldb set ld nop ld ld ldw ldw ei (dma0v),i2s_vector (intedma01),xxH (i2sctl0),xxxxH (i2sctl1),xxxxH xx Instruction (hdmas0),2000H (hdmad0),i2sbuf (hdmaca0),16 (hdmacb0),512 (hdmam0),0AH 0,(hdmae) (dmar),01H Comments ; Source address = 2000H ; Destination address = i2sbuf ; Counter A = 16 ; Counter B = 512 (32768/64) ; Transfer mode = source INC, 4 bytes ; Enable DMA channel 0. ; Transfer the first 64 bytes by DMA soft start. ; ; INTI2S = DMA0 ; INTDMA level = x ; Set operation mode for I2S. ; Start I2S transmission. ; Enable CPU interrupts. (b) INTDMA0 interrupt routine No 1 2 3 4 5 6 7 8 9 10 11 reti ; res : : : : Instruction 0,(hdmae) Comments ; Disable DMA channel 0. 92CF26A-98 2007-11-21 TMP92CF26A 3.6.5 Note In case of using S/W start with HDMA, transmission start is to set to "1" DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus occupation once with HDMATR function. We recommend to use HDMACBn register (counter value) to confirm flag of transmission end. 92CF26A-99 2007-11-21 TMP92CF26A 3.6.6 Considerations for Using More Than One Bus Master In the TMP92CF26A, the LCD controller, SDRAM controller, and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these functions to operate smoothly. To facilitate explanation of DMA operation performed by each bus master, the DMA transfer operation performed by the DMA controller is defined as "HDMA", the display RAM read operation performed by the LCD controller as "LDMA", and the SDRAM auto refresh operation performed by the SDRAM controller as "ARDMA". The following explains various cases where two or more bus masters may operate at the same time. (1) CPU + HDMA The DMA controller performs DMA transfer (HDMA) after issuing a bus request to the CPU and getting a bus acknowledgement. The DMA controller may be active while the CPU is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere with the CPU operation. However, if HDMA is started while the CPU is active, the CPU cannot execute instructions while HDMA is being performed. Before activating the DMA controller, therefore, it is necessary to estimate the CPU stop time (defined as "tSTOP (HDMA)") based on the transfer time, transfer start interval, and number of channels to be used. CPU bus stop rate = tSTOP (HDMA)[s] / HDMA start interval [s] HDMA start interval [s] = HDMA start interrupt period [s] Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also possible to start HDMA by software. tSTOP (HDMA) [s] = (Source read time + Destination write time) x Transfer count + state/byte Memory Type Read / Write Read Write Internal RAM 1/4 (Note 1) External SDRAM 16-bit bus Burst 1 / 2 1 word 6 / 2 Burst 1 / 2 1 word 3 / 2 (Note 2) (Note 2) (Note 2) (Note 2) External SRAM 16-bit bus 2/2 2/2 (Note 3) External SRAM 8-bit bus 2/1 2/1 (Note 3) 1/4 (Note 3) (Note 3) Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state. Note 2: The transfer speed varies depending on the combination of source and destination. a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access) is possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4 states are needed at the end of each burst access. b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used. Note 3: In the case of 0 waits state/byte I/O Type Read / Write Read Write I2S - 2/4 NANDF 2/2 2/2 USB 2/2 2/2 SPI 2/4 2/4 92CF26A-100 2007-11-21 TMP92CF26A Sample 1: Calculation example for CPU + HDMA Conditions: CPU operation speed (fSYS) I2S data transfer bit length : 60 MHz : 16 bits I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz) DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S Calculation example: DMAC source data read time: Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.) DMAC destination write time: I2S register write time = 2 states/4 bytes Transfer count To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as follows: 5 Kbytes/4 bytes = 1280 [times] Since I2S generates an interrupt for every 64 bytes, the DMAC's counter A is set to 16 (64 bytes/4 bytes = 16 times) and counter B is set to 80. Note: Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state) occurs 80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead time of 2 states is also needed for each interrupt request, requiring additional 160 states in total. tSTOP (HDMA) = (((1 + 2) x 16) x 80) + 80 + 160) / fSYS [S] = 68 [S] HDMA start interval [s] = 1 / I2S sampling frequency [Hz] x (64 / 16 ) = 83.33 [mS] CPU bus stop rate = tSTOP (HDMA) [s] / HDMA start interval [s] = 68 [S] / 83.33 [mS] = 0.08 [%] 92CF26A-101 2007-11-21 TMP92CF26A (2) CPU + LDMA The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the CPU and getting a bus acknowledgement. If LDMA is not performed properly, the LCD display function cannot work properly. Therefore, LDMA must have higher priority than the CPU. While LDMA is being performed, the CPU cannot execute instructions. To display data on the LCD using the LCD controller, it is necessary to estimate to what degree LDMA would interfere with the CPU operation based on the display RAM type, display RAM bus width, LCDD type, display pixel count, and display quality. The time the CPU stops operation while the LCD controller transfers data for one line is defined as "tSTOP (LDMA)", which is calculated as shown below for each display mode. tSTOP (LDMA) = (SegNum x K / 8) x tLRD 16-bit external SRAM Internal RAM SegNum K Monochrome 4 gray scales 16 gray scales 256 colors 4096 colors 65536 colors 262144/16777216 colors K = 12 K = 16 K = 24 : tLRD = (2 + wait count) / fSYS [Hz] / 2 : tLRD = 1 / fSYS [Hz] / 4 : Number of segments to be displayed : Number of bits needed for displaying 1 pixel K=1 K=2 K=4 K=8 16-bit external SDRAM : tLRD= 1 / fSYS [Hz] / 2 Note 1: When SDRAM is used, the overhead time is added as shown below. tSTOP [s] = (SegNum x K/8) x tLRD + ((1/fSYS) x 8) Note 2: When internal RAM is used, the overhead time is added as shown below. tSTOP [s] = ( SegNum x K/8 )x tLRD + (1/fSYS) The CPU bus stop rate indicates what proportion of the 1-line data update time tLP is taken up by tSTOP (LDMA) and is calculated as follows: CPU bus stop rate = tSTOP (LDMA) [s] / LHSYNC [period: s] 92CF26A-102 2007-11-21 TMP92CF26A Sample2: Calculation examples for CPU + LDMA Conditions 1: CPU operation speed (fSYS) Display RAM Display size Display quality Refresh rate Calculation example 1: tSTOP (LDMA) = ((SegNum x K / 8) x tLRD) + (1 / fSYS [Hz]) = ((320 x 16 / 8) x 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz]) = ((640) x 16.67 [ns] / 4) + 16.67 [ns] = 2.68 [s] LHSYNC [period: s] CPU bus stop rate = 1/70 [Hz] / (COM+20=260) = 54.95 [s] = tSTOP (LCD)[s] / LHSYNC [period: s] = 2.68 [s] / 54.95 [s] = 4.88 [%] : 60 MHz : Internal RAM : QVGA (320seg x 240com) : 65536 colors (TFT) : 70 Hz (including 20 clocks of dummy cycles) Conditions 2: CPU operation speed (fSYS) Display RAM Display size Refresh rate : 10 MHz : 16-bit external SRAM (0 waits) : QVGA (240seg x 320com) : 100 Hz (0 dummy cycles) Display quality : 4096 colors (STN) Calculation example 2: tSTOP (LDMA) = (SegNum x K / 8) x tLRD = (240 x 12 / 8) x (2 + wait count) / fSYS [Hz] / 2 = (360) x 200 [ns] / 2 = 36 [s] LHSYNC [period: s] CPU bus stop rate = 1/100 [Hz] / (COM = 240) = 41.67 [s] = tSTOP (LCD)[s] / LHSYNC [period: s] = 36 [s] / 41.67 [s] = 86.40 [%] 92CF26A-103 2007-11-21 TMP92CF26A (3) CPU + LDMA + ARDMA The SDRAM controller owns the bus not only when SDRAM is used as the LCD display RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller occupies the bus (ARDMA) while it refreshes SDRAM data by the auto refresh function. No special consideration is needed for the ARDMA time normally as it ends within several clocks per specified number of states. However, if the LCD controller occupies the bus continuously, ARDMA cannot be executed at normal intervals and refresh data is stored in a counter specifically provided in the SDRAM controller. In this case, ARDMA is executed successively after the LCD controller releases the bus. The priorities among the three bus masters should be set in the order of LCDC > SDRAMC > CPU. The time the CPU stops operation while the LCD controller and SDRAM controller are transferring data for one line is defined as "tSTOP (LDMA ARDMA)", which is calculated as follows: tSTOP (LDMAARDMA) = tSTOP (LDMA)[s] - (tSTOP (LDMA)[s] / AR interval [s] x 2 / fSYS [Hz]) CPU bus stop rate = tSTOP (LDMAARDMA)[s] / LHSYNC [period: s] Auto Refresh Intervals SDRCR 0 0 0 0 1 1 1 1 Unit: [s] SRS1 0 0 1 1 0 0 1 1 SRS0 0 1 0 1 0 1 0 1 Auto Refresh Interval (states) 47 78 156 312 468 624 936 1248 Frequency (System Clock) 6 MHz 7.8 13.0 26.0 52.0 78.0 104.0 156.0 208.0 10MHz 4.7 7.8 15.6 31.2 46.8 62.4 93.6 124.8 20MHz 2.4 3.9 7.8 15.6 23.4 31.2 46.8 62.4 40MHz 1.18 1.95 3.90 7.80 11.70 15.60 23.40 31.20 60MHz 0.78 1.30 2.60 5.20 7.80 10.40 15.60 20.80 80MHz 0.59 0.98 1.95 3.90 5.85 7.80 11.70 15.60 92CF26A-104 2007-11-21 TMP92CF26A Sample3: Calculation example for CPU + LDMA + ARDMA Conditions: CPU operating speed (fSYS) Display RAM Display size Display quality Refresh rate SDRAM auto refresh Calculation example: tSTOP (LDMA) =((SegNum x K / 8) x tLRD) + (8 / fSYS [Hz]) = ((320 x16 / 8) x 1 / fSYS [Hz] / 2) + (8 / fSYS [Hz]) = ((640) x 16.67 [ns] / 2) + 133.33 [ns] = 5.47 [s] LHSYNC [period:s] = 1/70 [Hz] / (COM + 20 = 260) = 54.95 [s] : 60 MHz : 16-bit external SDRAM : QVGA (320seg x 240com) : 65536 colors (TFT) : 70 Hz (including 20 clocks of dummy cycles) : Every 936 states (15.6 s) Since SDRAM is auto-refreshed once or less in 5.47 [s]: tSTOP (ARDMA) CPU bus stop rate = 2 / fSYS [Hz] = 33.33 [ns] = tSTOP (LDMAARDMA) [s] / LHSYNC [period:s] = (5.47 [s] + 33.33 [ns]) / 54.95 [s] = 10.01 [%] 92CF26A-105 2007-11-21 TMP92CF26A (4) CPU + LDMA+ ARDMA + HDMA This is a case in which all the bus masters are active at the same time. Since the LCD display function cannot work properly if the LCD controller cannot perform LDMA properly, the priorities among the four bus masters should be set in the order of LDMA > ARDMA > HDMA > CPU. Before calculating the CPU bus stop rate, the conditions for proper LCD display shall be considered first. Setup time 1 LHSYNC LCP0 LD-bus LDMA1 HDMA (Worst case) LDMA2 Setup time 2 The above diagram shows the LHSYNC signal, LCP0 signal, and LD-bus signal for transferring data from the LCD controller to the LCD driver, and the transfer operation (LDMA1) for reading data from the display RAM into the FIFO buffer in the LCD controller. LDMA is started immediately after data has been transferred to the LCD driver. If HDMA is started immediately before LDMA1 is started, LDMA must wait until HDMA has finished before it can be started (LDMA2). LDMA2 must finish operation before the LCD driver output for the next stage is started. LHSYNC [period: s] - LCD driver data transfer time [s] - tSTOP (LCD) [s] = HDMA continuous time [s] + CPU operation time [s] In the case of STN display LCD driver data transfer time [s] = SegNum/8x(1/fSYS) x (LD bus transfer speed) In the case of TFT display LCD driver data transfer time [s] = SegNumx(1/ fSYS) x (LD bus transfer speed) 92CF26A-106 2007-11-21 TMP92CF26A Sample 4: Calculation example for CPU + LDMA+ ARDMA + HDMA Conditions: CPU operation speed (fSYS) Display RAM Display quality Refresh rate SDRAM Auto Refresh SDRAM HDMA : 60 MHz : QVGA (320seg x 240com) : 65536 colors (TFT) : 70 Hz (including 20 clocks of dummy cycles) : Every 936 states (15.6 s) : 16-bit width : Transfers 5 Kbytes from internal RAM to I2S Calculation example: tSTOP (LDMA) =((SegNum x K / 8) x tLRD) + (1 / fSYS [Hz]) = ((320 x16 / 8) x 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz]) = ((640) x16.67 [ns] / 4) + 16.67 [ns] = 2.68 [s] LHSYNC [period: s] = 1/70 [Hz] /(COM+20 = 260) = 54.95 [s] tSTOP (HDMA) = (((1 + 2) x 16) x 80) + 80 + 160) / fSYS [s] = 68 [s] LCD driver data transfer time [s] = SegNum x (1/ fSYS) x (LD bus transfer speed) = 320 x (1/60 MHz) x 16 = 85 [s] Since LHSYNC [period: s] < LCD driver data transfer time [s], this setting is not possible. When the transfer speed is changed to x4, the LCD driver data transfer time is calculated as follows: (The transfer speed should be adjusted according to the required specifications.) LCD driver data transfer time [s] = SegNum x (1/ fSYS) x (LD bus transfer speed) = 320 x (1 / 60MHz) x 4 = 21.3 [s] LHSYNC [period: s] - LCD driver data transfer time [s] - tSTOP (LDMA) = 54.95 [s] - 21.3 [s] - 2.68 [s] = 30.94 [s] To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time) must be set to 30.92 [S] or less. Although transferring all 5 Kbytes from the internal RAM to I2S requires tSTOP (HDMA) = 68 [s], the maximum HDMA time should be limited by using the HDMATR register. 92CF26A-107 2007-11-21 TMP92CF26A HDMATR Register 7 HDMATR (097FH) bit Symbol Read/Write Reset State 0 Timer Function operation 0: Disable 1: Enable 0 0 0 DMATE 6 DMATR6 5 DMATR5 4 DMATR4 3 DMATR3 0 2 DMATR2 0 1 DMATR1 0 0 DMATR0 0 R/W Maximum bus occupancy time setting The value to be set in Note: Read-modify-write instructions can be used on this register. By writing "87H" to the HDMATR register, the maximum HDMA time is set to 29.9 [s] (256 x 7 x (1 / fSYS)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than LHSYNC [period:s] = 54.95 [s], it is assumed that HDMA transfer occurs once during LHSYNC [period:s]. Since SDRAM is auto-refreshed once or less in 5.47 [s]: tSTOP (ARDMA) = 2 / fSYS [Hz] = 33.33 [ns] The time LDMA, ARDMA, and HDMA all occupy the bus is defined as: tSTOP (LDMAARDMAHDMA) Based on the above, the CPU bus stop rate is calculated as follows: CPU bus stop rate = tSTOP (LDMAARDMAHDMA) [s] / LHSYNC [period:s] = (5.47 [s] + 33.33 [ns]+ 29.9 [s]) / 54.95 [s] = 64.42 [%] Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is forcefully terminated at 29.9 [s]. 92CF26A-108 2007-11-21 TMP92CF26A Sample 5: Calculation example when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) Conditions: CPU operation speed (fSYS) Display RAM Display size Display quality Refresh rate HDMA Calculation example: tSTOP (LCD) = ((SegNum x K/8) x tLRD) + (1/fSYS [Hz]) = ((320 x 24/8) x 1/fSYS [Hz]/4) + (1/fSYS [Hz]) = ((960) x 12.5 [nS]/4) + 12.5 [nS] = 3.0125 [S] LHSYNC [period: S] = 1/70 [Hz]/ (COM+20) = 54.9 [S] tSTOP (HDMA) = (((2 + 1) x 4) x 57600) + 28800 + 14400)/ fSYS [S] = 9180 [S] : 80MHz : Internal RAM : QVGA (320seg x 240com) : 16777216 color (TFT) : 70Hz : Transfers 225 Kbytes from internal RAM to SDRAM LCD driver data transfer time [S] = SegNum x (1/ fSYS) x (LD bus transfer speed) = 320 x (1/80MHz) x 8 = 32 [S] LHSYNC [cycle S] - LCD driver data transfer time [S] - tSTOP (LCD) = 54.9 [S] - 32 [S] - 3.0125 [S] = 19.8875 [S] To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time) must be set to 19.8875 [S] or less. Although transferring all 225 Kbytes from the internal RAM to SDRAM requires tSTOP (HDMA) = 9180 [s], the maximum HDMA time should be limited by using the HDMATR register. HDMATR register 7 HDMATR (097FH) Bit Symbol Read/Write Reset State Function 0 Timer operation 0: Disable 1:Enable 0 0 0 DMATE 6 DMATR6 5 DMATR5 4 DMATR4 R/W 3 DMATR3 0 2 DMATR2 0 1 DMATR1 0 0 DMATR0 0 Maximum bus occupancy time setting The value to be set in Note: Read-modify-write instructions can be used on this register. By writing "86H" to the HDMATR register, the maximum HDMA time is set to 19.2[s] (256 x 6 x (1 / fSYS)). Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is forcefully terminated at 19.2 [s]. 92CF26A-109 2007-11-21 TMP92CF26A 3.7 Function of ports The TMP92CF26A I/O port pins are shown in Table 3.7.1. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.7.2 lists the I/O registers and their specifications. Table 3.7.1 Port Functions (1/3) (R: PD= with programmable pull-down resistor, U= with pull-up resistor) Port Name Port 1 Port 4 Port 5 Port 6 Pin Name P10 to P17 P40 to P47 P50 to P57 P60 to P67 P70 P71 P72 P73 P74 P75 Number of Pins 8 8 8 8 1 1 1 1 1 1 I/O I/O Output Output I/O Output I/O I/O I/O I/O I/O R - - - - - - - - - - - - - - - - - - - - - - I/O Setting bit bit bit bit (Fixed) bit bit bit bit bit Pin Name for built-in function D8 to D15 A0 to A7 A8 to A15 A16 to A23 RD WRLL , NDRE WRLU , NDWE Port 7 EA24 EA25 R/ W , NDR/ B WAIT CS0 CS1, SDCS CS2 , CSZA CS3 , CSXA CSZB CSZC P76 Port 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 I/O Output Output Output Output Output Output Output Output I/O I/O I/O Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Input Input Input Input bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) bit bit bit (Fixed) (Fixed) (Fixed) bit bit bit bit bit bit bit bit bit bit bit bit bit bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) P80 P81 P82 P83 P84 P85 P86 P87 CSZD , ND0CE CSXB , ND1CE Port 9 P90 P91 P92 P96 P97 TXD0 RXD0 SCLK0, CTS0 INT4, PX PY KI0 to KI7 INT0 INT1, TA0IN INT2 INT3, TA2IN EA26 EA27 EA28 KO8 I2S0CKO I2S0DO I2S0WS I2S1CKO I2S1DO I2S1WS SDCLK AN0 to AN1 AN2, MX AN3, ADTRG , MY AN4 to AN5 PD - Port A Port C PA0 to PA7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 U - - - - - - - - - - - - - - - - - - - Port F PF0 PF1 PF2 PF3 PF4 PF5 PF7 Port G PG0 to PG1 PG2 PG3 PG4 to PG5 92CF26A-110 2007-11-21 TMP92CF26A Table 3.7.1 Port Functions (2/3) Port Name Port J Pin Name PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 Number of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 8 6 1 1 1 1 1 1 1 1 1 8 1 1 1 I/O Output Output Output Output Output I/O I/O Output Output Output Output Output Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Output I/O I/O I/O Output I/O I/O R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O Setting (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) bit bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) bit bit bit bit bit bit (Fixed) (Fixed) bit bit bit bit bit bit bit bit bit bit bit (Fixed) (Fixed) bit bit bit bit bit bit Pin Name for built-in function SDRAS , SRLLB SDCAS , SRLUB SDWE , SRWR SDLLDQM SDLUDQM NDALE NDCLE SDCKE LCP0 LLOAD LFR LVSYNC LHSYNC LGOE0 LGOE1 LGOE2 LD0 to LD7 MLDALM, TA1OUT Port K PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 Port L Port M PL0 to PL7 PM1 PM2 PM7 ALARM , MLDALM PWE KO0 to KO7 TA3OUT TA5OUT INT5, TA7OUT INT6, TB0IN0 INT7, TB1IN0 TB0OUT0 TB1OUT0 SPDI SPDO Port N Port P PN0 to PN7 PP1 PP2 PP3 PP4 PP5 PP6 PP7 Port R PR0 PR1 PR2 PR3 SPCS SPCLK LD8 to LD15 LD16 to LD20 , LD22 LD21 LD23, EO_TRGOUT SCLK0 - - - - Port T Port U PT0 to PT7 PU0 to PU4 ,PU6 PU5 PU7 Port V PV0 PV1 PV2 PV3 PV4 PV6 PV7 SDA SCL - Port W Port X PW0 to PW7 PX4 PX5 PX7 CLKOUT, LDIV X1USB - 92CF26A-111 2007-11-21 TMP92CF26A Table 3.7.1 Port Functions (3/3) Port Name Port Z Pin Name PZ0 PZ1 PZ2 PZ3 PZ4 PZ5 PZ6 PZ7 Number of Pins 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - I/O Setting bit bit bit bit bit bit bit bit Pin Name for built-in function EI_PODDATA EI_SYNCLK EI_PODREQ EI_REFCLK EI_TRGIN EI_COMRESET EO_MCUDATA EO_MCUREQ 92CF26A-112 2007-11-21 TMP92CF26A Table 3.7.2 I/O Port and Specifications (1/4) Port Port 1 X: Don't care I/O register Pn X X X X X X X X X X X X X 1 0 1 0 X X X X X X X X X X X X X X X X X X X X None Pin name P10 toP17 Input port Output port Specification PnCR 0 1 X None None None None 0 1 X 1 0 None 1 1 1 1 1 0 0 PnFC PnFC2 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 X 1 0 1 1 X 1 1 1 1 1 1 0 None 0 1 0 1 1 0 1 None 0 1 0 1 None None None None D8 to D15 bus Port 4 Port 5 Port 6 P40 to P47 P50 to P57 P60 to P67 Output port A0 to A7 Output Output port A8 to A15 Output Input port Output port A16 to A23 Output Port 7 P70 to P76 P71 to P76 P70 P71 P72 P73 P74 P75 P76 Port 8 P80 to P87 P80 P81 P82 Output port Input port RD Output WRLL Output NDRE Output WRLU Output NDWE Output None EA24 Output EA25 Output R/ W Output NDR/B Input WAIT Input Output port CS0 Output CS1 Output SDCS Output CS2 Output CSZA Output SDCS Output P83 P84 P85 P86 P87 CS3 Output CSXA Output CSZB Output CSZC Output CSZD Output ND0CE Output CSXB Output ND1CE Output 92CF26A-113 2007-11-21 TMP92CF26A Table3.7.2 I I/O Port and Specifications (2/4) Port Port 9 X: Don't care I/O register Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 X X X Pin name P90, P92 P91 P96 P97 P90 to P92 P90 P92 P96 Input port Specification PnCR 0 0 None None 1 1 1 1 0 None None 0 1 0 0 1 0 0 1 0 0 0 1 0 1 None X X X X X X None PnFC PnFC2 0 None 0 None 0 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 None None None None None None 0 0 1 0 0 None None Input port, RXD0 Input Input port Input port Output port TXD0 Output TXD0 Output (Open-drain) SCLK0 Output SCLK0, CTS0 Input INT4 Input Input port KI0 to KI7 Input Input port Output port INT0 Input INT1 Input TA0IN Input INT2 Input INT3 Input TA2IN Input EA26 Output EA27 Output EA28 Output KO8 Output (Open-drain) Input port Output port Output port I2S0CKO Output I2S0DO Output I2S0WS Output I2S1CKO Output I2S1DO Output I2S1WS Output SDCLK Output Port A Port C PA0 to PA7 PC0 to PC7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Port F PF0 to PF5 PF0 to PF5 PF7 PF0 PF1 PF2 PF3 PF4 PF5 PF7 92CF26A-114 2007-11-21 TMP92CF26A Table3.7.2 I/O Port and Specifications (3/4) Port Port G X: Don't care I/O register Pin name PG0 to PG5 PG3 PG2 PG3 Input port Specification Pn AN0 to AN5 Input ADTRG Input MX Output MY Output Input port Output port Output port Note: Note: X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X 0 1 None 1 1 0 1 0 1 0 1 None 0 1 None None None 1 None None 0 1 None PnCR PnFC PnFC2 0 X None 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 None Port J PJ5 to PJ6 PJ5 to PJ6 PJ0 to PJ4, PJ7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 SDRAS , SRLLB Output SDCAS , SRLUB Output SDWE , SRWR Output SDLLDQM Output SDLUDQM Output NDALE Output NDCLE Output SDCKE Output Output port LCP0 output LLOAD output LFR output LVSYNC output LHSYNC output LGOE0 output LGOE1 output LGOE2 output Output port LD0 to LD7 Output Output port TA1OUTOutput MLDALM Output None Port K PK0 to PK7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 None Port L Port M PL0 to PL7 PL0 to PL7 PM1 to PM2 PM1 PM2 PM7 None MLDALM Output ALARM Output PWE Output Input port Output port (CMOS Output) KO Output (Open-drain Output) None Port N PN0 to PN7 None Port P PP1 to PP5 PP1 to PP5 PP6 to PP7 PP1 PP2 PP3 PP4 PP5 PP6 PP7 Input port Output port Output port TA3OUT output TA5OUT output INT5 input TA7OUT output INT6 input TB0IN0 input INT7 input TB1IN0 input TB0OUT0 output TB1OUT1 output None Note: Case of using touch screen 92CF26A-115 2007-11-21 TMP92CF26A Table 3.7.2 I/O Port and Specifications (4/4) Port Port R X: Don't care I/O register Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X Pin name PR0 to PR3 PR0 to PR3 PR0 PR1 PR2 PR3 Input port Output port SPDI Input Specification PnCR 0 1 0 1 1 1 0 1 1 0 1 1 X 0 1 0 1 1 1 1 1 1 1 0 1 0 None 1 None 0 0 1 X X X X X X X X PnFC PnFC2 0 0 1 1 1 1 0 0 1 0 0 1 X 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 X X X X X X X X None None None None 0 1 None 0 1 0 1 None None None None SPDO Output SPCS Output SPCLK Output Input port Output port LD8 to LD15 Output Input port Output port LD16 to LD23 Output EO_TRGOUT ( DBGE = "0") Note: Input port Output port Input port Output port Output port (Open-drain) SCLK0 Output SDA I/O SDA I/O (Open-drain) SCL I/O SCL I/O (Open-drain) Input port Output port Input port Output port Output port CLKOUT Output LDIV Output X1USB Input Input port Output port EI_PODDATA ( DBGE = "0") Note: EI_SYNCLK ( DBGE = "0") Note: EI_PODREQ ( DBGE = "0") Note: EI_REFCLK ( DBGE = "0") Note: EI_TRGIN ( DBGE = "0") Note: EI_COMRESET ( DBGE = "0") Note: EO_MCUDATA ( DBGE = "0") Note: EO_MCUREQ ( DBGE = "0") Note: Port T PT0 to PT7 PT0 toPT7 PT0 to PT7 Port U PU0 to PU7 PU0 to PU7 PU0 to PU7 PU7 Port Va PV0 to PV2 PV0 to PV4 PV6 to PV7 PV6 to PV7 PV6 to PV7 PV0 PV6 PV7 Port W PW0 to PW7 PW0 to PW7 Port X PX5, PX7 PX4 PX5, PX7 PX4 PX5 Port Z PZ0 to PZ7 PZ0 PZ1 PZ2 PZ3 PZ4 PZ5 PZ6 PZ7 Note: When Debug mode, it is set to the Debug pin regardless of port setting. 92CF26A-116 2007-11-21 TMP92CF26A 3.7.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins: AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after reset is released Don't use this setting Data bus (D8 to D15) Don't use this setting Input port (P10 to P17) P1CR Register P1FC Register External write enable P1 Register S 0 D8 to D15 S 1 Selector P10 to P17 (D8 to D15) Port read data D8 to D15 1 0 Selector External read enable Figure 3.7.1 Port1 92CF26A-117 2007-11-21 TMP92CF26A Port 1 register 7 P1 bit Symbol P17 (0004H) Read/Write System Reset State Hot Reset State 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to "0") - Port 1 Control register 7 P1CR bit Symbol P17C (0006H) Read/Write System Reset State Hot Reset State Function 6 P16C 5 P15C 4 P14C W 3 P13C 2 P12C 1 P11C 0 P10C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output Port 1 Function register 7 P1FC bit Symbol (0007H) Read/Write System Reset State (Note2) Hot Reset State Function 6 5 4 3 2 1 0 P1F W 0/1 - 0: Port 1:Data bus (D8 to D15) Port 1 Drive register 7 P1DR bit Symbol P17D (0081H) Read/Write System Reset State Hot Reset State Function 6 P16D 5 P15D 4 P14D R/W 3 P13D 2 P12D 1 P11D 0 P10D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for P1CR, P1FC. Note2: It is set to "Port" or "Data bus" by AM pins state. Figure 3.7.2 Register for Port1 92CF26A-118 2007-11-21 TMP92CF26A 3.7.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins: AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after reset is released Don't use this setting Address bus (A0 to A7) Don't use this setting Output port (P40 to 47) P4FC Register P4 Register S 0 A0 to A7 1 P40 to P47 (A0 to A7) Selector Read data Figure 3.7.3 Port4 92CF26A-119 2007-11-21 TMP92CF26A Port 4 register 7 P4 (0010H) bit Symbol Read/Write System Reset State Hot Reset State P47 6 P46 5 P45 4 P44 R/W 3 P43 2 P42 1 P41 0 P40 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Port 4 Function register 7 P4FC (0013H) bit Symbol Read/Write System Reset State (Note2) Hot Reset State Function P47F 6 P46F 5 P45F 4 P44F W 3 P43F 2 P42F 1 P41F 0 P40F 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0:Port 1:Address bus (A0 to A7) Port 4 Drive register 7 P4DR (0084H) bit Symbol Read/Write System Reset State Hot Reset State Function P47D 6 P46D 5 P45D 4 P44D R/W 3 P43D 2 P42D 1 P41D 0 P40D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for P4FC. Note2: It is set to "Port" or "Data bus" by AM pins state. Figure 3.7.4 Register for Port1r 92CF26A-120 2007-11-21 TMP92CF26A 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins: AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after reset is released Don't use this setting Address bus (A8 ~ A15) Don't use this setting Output port (P50 ~ P57) P5FC Register P5 Register S 0 A8 to A15 Read data P50 to P57 (A8 to A15) 1 Selector Figure 3.7.5 Port5 92CF26A-121 2007-11-21 TMP92CF26A Port 5 register 7 P5 (0014H) bit Symbol Read/Write System Reset State Hot Reset State P57 6 P56 5 P55 4 P54 R/W 3 P53 2 P52 1 P51 0 P50 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Port 5 Function register 7 P5FC (0017H) bit Symbol Read/Write System Reset State (Note2) Hot Reset State Function P57F 6 P56F 5 P55F 4 P54F W 3 P53F 2 P52F 1 P51F 0 P50F 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0:Port 1:Address bus (A8 to A15) Port 5 Drive register 7 P5DR (0085H) bit Symbol Read/Write System Reset State Hot Reset State Function P57D 6 P56D 5 P55D 4 P54D R/W 3 P53D 2 P52D 1 P51D 0 P50D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for P5FC. Note2: It is set to "Port" or "Data bus" by AM pins state. Figure 3.7.6 Register for Port5 92CF26A-122 2007-11-21 TMP92CF26A 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function as an address bus (A16 to A23). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 6 to the following function pins: AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after reset is released Don't use this setting Address bus(A16 ~ A23) Don't use this setting Input port(P60 ~ P67) P6CR Register P6FC Register P6 Register S 0 A16 to A23 S P60 to P67 (A16 to A23) 1 Selector Read data 1 0 Selector Figure 3.7.7 Port6 92CF26A-123 2007-11-21 TMP92CF26A Port 6 register 7 P6 (0018H) bit Symbol Read/Write System Reset State Hot Reset State P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Data from external port (Output latch register is cleared to "0") - Port 6 Control register 7 P6CR (001AH) bit Symbol Read/Write System Reset State Hot Reset State Function P67C 6 P66C 5 P65C 4 P64C W 3 P63C 2 P62C 1 P61C 0 P60C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0:Input 1:Output Port 6 Function register 7 P6FC (001BH) bit Symbol Read/Write System Reset State (Note2) Hot Reset State Function P67F 6 P66F 5 P65F 4 P64F W 3 P63F 2 P62F 1 P61F 0 P60F 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0/1 - 0: Port 1:Address bus (A16 to A23) 7 P6DR (0086H) bit Symbol Read/Write System Reset State Hot Reset State Function P67D 6 P66D Port 6 Drive buffer register 5 4 3 P65D P64D R/W 2 P62D 1 P61D 0 P60D P63D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for P6CR, P6FC. Note2: It is set to "Port" or "Data bus" by AM pins state. Figure 3.7.8 Register for Port 6 92CF26A-124 2007-11-21 TMP92CF26A 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function as interface-pins for external memory. A reset initializes P70 pin to output port mode, and P71 to P76 pins to input port mode. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7 to the following function pins: Initial setting of P70 pin AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after reset is released Don't use this setting RD pin Don't use this setting Output port (P70) P7FC register P7 register RD 0 1 S P70 ( RD ) Selector Port read data P7CR register P7FC register P7 register NDRE , NDWE WRLL , WRLU 0 1 Selector S1 0 Selector S 0S 1 Selector P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) Port read data Figure 3.7.9 Port7 92CF26A-125 2007-11-21 TMP92CF26A P7CR register P7FC register S 0 1 S1 Selector P73 (EA24) P74 (EA25) P7 register EA24, EA25 Read data 0 Selector P7CR register P7FC register P7 register R/W Port read data S1 0 Selector 0S 1 Selector P75(R/W, NDR /B ) NDR/ B P7CR register P7FC register P7 register Port read data WAIT P76 ( WAIT ) Figure 3.7.10 Port7 92CF26A-126 2007-11-21 TMP92CF26A Port 7 register 4 P74 7 P7 (001CH) bit Symbol Read/Write System Reset State Hot Reset State 6 P76 5 3 P73 2 P72 1 P71 0 P70 P75 R/W Data from external port Data from external port Data from external port (Output latch register is (Output latch register is (Output latch register is set to "1") cleared to "0") set to "1") - - - 1 - 7 P7CR (001EH) bit Symbol Read/Write System Reset State Hot Reset State Function 6 P76C Port 7 Control register 5 4 3 P75C P74C W P73C 2 P72C 1 P71C 0 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output 7 P7FC (001FH) bit Symbol Read/Write System Reset State Hot Reset State Function 6 P76F Port 7 Function register 5 4 3 P75F P74F P73F W 2 P72F 1 P71F 0 P70F 0 - 0 - 0 - 0 - 0 - 0 - 0/1 Note3: - 0:Port 1: WAIT Refer to following table 0:Port 1: NDWE at 0:Port 1: NDRE at 0:Port 1: RD 7 P7DR (0087H) bit Symbol Read/Write System Reset State Hot Reset State Function P73 setting < 6 P76D Port 7 Drive register 5 4 3 P75D P74D P73D R/W 2 P72D 1 P71D 0 P70D 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode P72 setting < P71 setting (at NDWE Output (at P76 setting P75 setting P74 setting Input Port WAIT Input Output Port Reserved Input Port NDR/ B Input Output Port R/W Output Input Port Reserved Output Port EA25Output Note1: A read-modify-write operation cannot be performed for P7CR, P7FC. Note2: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch. Order Registser bit2 bit1 -----------------------------------------------------(1) P7 0 0 (2) P7FC 1 1 (3) P7CR 1 1 Note3: It is set to "Port" or "Data bus" by AM pins state. Figure 3.7.11 Register for Port 7 92CF26A-127 2007-11-21 TMP92CF26A 3.7.6 Port 8 (P80 to P87) Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to "0" and the output latches of P80 to P81, P83 to P87 to "1". But if it is started at boot mode (AM [1:0]= "11"), output latch of P82 is set to "1". Port 8 can also be set to function as an interface-pin for external memory using function register P8FC. Writing "1" in the corresponding bit of P8FC and P8FC2 enables the respective functions. Resetting P8FC to "0" and P8FC2 to "0", sets all bits to output ports. Reset Function control2 P8FC2 write Function control P80 ( CS0 ) P81 ( CS1, SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 , CSXA ) P84 ( CSZB ) P85 ( CSZC ) P86 ( CSZD , ND0CE ) P87 ( CSXB , ND1CE ) Internal data bus P8FC write S Output latch Selector P8 write CS0 , SDCS , SDCS , CSXA , CSZB , CSZC , ND0CE , ND1CE P8 read "1", SDCS , CSZA , CSXA ,"1", "1", "1", "1" CS0 , CS1, CS2 , CS3 , CSZB , CSZC , CSZD , CSXB Figure 3.7.12 Port 8 92CF26A-128 2007-11-21 TMP92CF26A Port 8 register 4 P84 R/W 1 - 7 P8 (0020H) bit Symbol Read/Write System Reset State Hot Reset State P87 6 P86 5 3 P83 2 P82 1 P81 0 P80 P85 1 - 1 - 1 - 1 - 0 (Note3) - 1 - 1 - 7 P8FC (0023H) bit Symbol Read/Write System Reset State Hot Reset State Function P87F 6 P86F Port 8 Function register 5 4 3 P85F P84F W P83F 2 P82F 1 P81F 0 P80F 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Port 0: Port 0: Port 1: 0: Port 1: CSZB Refer to following table 0: Port 1: CS1 0: Port 1: CS0 7 P8FC2 (0021H) bit Symbol Read/Write System Reset State Hot Reset State Function P87F2 W 0 - 0: CSXB 1: ND1CE 6 P86F2 Port 8 Function registers 2 5 4 3 P83F2 2 P82F2 W 1 P81F2 0 0 - 0: CSZD 0 - 0 - 0 - 1: ND0CE Refer to following table 0: 7 P8DR (0088H) bit Symbol Read/Write System Reset State Hot Reset State Function P86 setting CSZD Output 6 P86D Port 8 Drive register 5 4 3 P85D P84D R/W P83D 2 P82D 1 P81D 0 P80D P87D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode P83 setting P82 setting CS3 Output CS2 Output SDCS Output ND0CE Output CSXA Output CSZA Output P87 setting CSXB Output ND1CE Output Note1: A read-modify-write operation cannot be performed for P8FC and P8FC2. Note2: Do not write "1" to P8 Figure 3.7.13 Register for Port 8 92CF26A-129 2007-11-21 TMP92CF26A 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on a bit basis using the control register. Each bit can be set individually for input or output. Resetting sets P90 to P92 to input port and all bits of output latch to"1". P96 to P97 are 2-bit general-purpose input port. Writing "1" the corresponding bits of P9FC enables the respective functions. Resetting resets the P9FC to "0", and sets all bits to input ports. (1) Port 90 (TXD0), Port 91 (RXD0), Port 92 (SCLK0, CTS0 ) Ports 90 to 92 are general-purpose I/O port. They also function as either SIO0. Each pin is detailed below. SIO mode (SIO0 module) P90 P91 P92 TXD0 (Data output) RXD0 (Data input) SCLK0 (Clock input or output) UART, IrDA mode (SIO0 module) TXD0 (Data output) RXD0 (Data input) CTS0 (Clear to send) Reset Direction control (on bit basis) P9CR write Function control (on bit basis) Internal data bus P9FC write S Output latch P9 write TXD0 output A S P90 (TXD0) Open-drain enable P9FC2 Selector B SB Selector P9 read A Figure 3.7.14 P90 92CF26A-130 2007-11-21 TMP92CF26A Reset Direction control (on bit basis) P9CRwrite Internal data bus Function control (on bit basis) P9FCwrite S Output latch P9 write SCLK0 output A S P91(RXD0) P92(SCLK0, CTS0 ) Selector B SB Selector P9 read A RXD0 input SCLK0 input CTS0 input Figure 3.7.15 P91, 92 Reset Function control TSICR0 Internal data bus AVCC P9FC write Switch for TSI typ.10 P9 read P96 (INT4,PX) P97 (PY) TSICR1 Only for P96 S INT4 Rising/Falling edge-ditection A De-bounce Circuit Selector B IIMC TSICR0 TSICR0 Pull-down resistor typ.50K Figure 3.7.16 Port 96,97 92CF26A-131 2007-11-21 TMP92CF26A Port 9 register 4 7 P9 (0024H) bit Symbol Read/Write System Reset State Hot Reset State P97 6 P96 5 3 2 P92 1 P91 0 P90 R Data from external port - R/W Data from external port (Output latch register is set to "1") - 7 P9CR (0026H) bit Symbol Read/Write System Reset State Hot Reset State Function 6 Port 9 control register 5 4 3 2 P92C 1 P91C W 0 P90C 0 - 0 - 0 - Refer to following table 7 P9FC (0027H) bit Symbol Read/Write System Reset State Hot Reset State Function 0: 6 P96F W 0 - Input Port 9 function register 5 4 3 2 P92F W 0 - 1 0 P90F W 0 - port 1: INT4 Refer to following table Refer to following table 7 P9FC2 (0025H) bit Symbol Read/Write System Reset State Hot Reset State Function - 6 Port 9 Function registers 2 5 4 3 2 - 1 0 P90F2 W 0 - 0:CMOS 1:Open-drain W 0 - W 0 - Always write "0" Always write "0" 7 P9DR (0089H) bit Symbol Read/Write System Reset State Hot Reset State Function P92 setting 6 P96D R/W Port 9 drive register 5 4 3 2 P92D 1 P91D R/W 0 P90D P97D 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode P91 setting Input port RXD0 Input P90 setting 0 1 Input port, CTS0 /SCLK0 Input Don't setting 1 Output port Note 1: A read-modify-write operation cannot be performed for P9CR, P9FC and P9FC2. Note 2: When setting P96 pin to INT4 input, set P9DR Figure 3.7.17 Register for Port 9 92CF26A-132 2007-11-21 TMP92CF26A 3.7.8 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also, as a Keyboard interface,operate a Key-on wake-up function. The various functions can each be enabled by writing a "1" to the corresponding bit of the Port A Function Register (PAFC). Resetting resets all bits of the register PAFC to "0" and sets all pins to be input port. INTKEY Rising edge -ditection Internal data bus PA0~PA7 8 input OR Reset KEY-ON ENABLE (on bit basis) PAFC write PA0 to PA7 (KI0 to KI7) PA read Pull-up resistor Figure 3.7.18 Port A When PAFC = "1", if the input of any of KI0-KI7 pins falls down, an INTKEY interrupt is generated. An INTKEY interrupt can be used to release all HALT modes. 92CF26A-133 2007-11-21 TMP92CF26A Port A register 7 PA (0028H) bit Symbol Read/Write System Reset State Hot Reset State PA7 6 PA6 5 PA5 4 PA4 R 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port - Port A Function register 7 PAFC (002BH) bit Symbol Read/Write System Reset State Hot Reset State Function PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 2 PA2F 1 PA1F 0 PA0F 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: KEY IN disable 1: KEY IN enable Port A Drive register 7 PADR (008AH) bit Symbol Read/Write System Reset State Hot Reset State Function PA7D 6 PA6D 5 PA5D 4 PA4D R/W 3 PA3D 2 PA2D 1 PA1D 0 PA0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note: A read-modify-write operation cannot be performed for PAFC. Figure 3.7.19 Register for Port A 92CF26A-134 2007-11-21 TMP92CF26A 3.7.9 Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latch register to "1". In addition to functioning as a general-purpose I/O port, Port C can also function as an input pin for timers (TA0IN, TA2IN), input pin for external interruption (INT0 to INT3), Extension address function (EA26, EA27, EA28) and output pin for Key (KO8). These settings are mode using the function register PCFC. The edge select for external interruption is determined by the IIMC register in the interruption controller. (1) PC0 (INT0), PC2 (INT2) Reset Direction control PCCR write Internal data bus Function control PCFC write S Output latch PC0 (INT0) PC2(INT2) PCwrite S B Selector PC read INT0 INT2 A Level/edge selection and Rising/Falling selection IIMC Figure 3.7.20 Port C0, C2 92CF26A-135 2007-11-21 TMP92CF26A (2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN) Reset Direction control PCCR write Internal data bus Function control PCFCwrite S Output latch PC1 (INT1,TA0IN) PC3 (INT3, TA2IN) PCwrite S B Selector PC read INT1 INT3 A Level/edge selection and Rising/Falling selection IIMC Figure 3.7.21 Port C1,C3 92CF26A-136 2007-11-21 TMP92CF26A (3) PC4 (EA26), PC5 (EA27), PC6 (EA28) Reset Direction control (on bit basis) PCCRwrite Function control (on bit basis) PCFC write S Output latch PC write EA26 EA27 EA28 S A Selector Internal data bus PC4(EA26) PC5(EA27) PC6(EA28) C SB Selector PC read A Figure 3.7.22 Port C4, C5, C6 (4) PC7 (KO8) Reset Direction control PCCR write Function control PCFC write Internal data bus S Output latch PC write SB Selector PC read A PC7(KO8) Open-drain enable Figure 3.7.23 Port C7 92CF26A-137 2007-11-21 TMP92CF26A Port C register 7 PC (0030H) bit Symbol Read/Write System Reset State Hot Reset State PC7 6 PC6 5 PC5 4 PC4 R/W 3 PC3 2 PC2 1 PC1 0 PC0 Data from external port (Output latch register is set to "1") - Port C control register 7 PCCR (0032H) bit Symbol Read/Write System Reset State Hot Reset State Function PC7C 6 PC6C 5 PC5C 4 PC4C W 3 PC3C 2 PC2C 1 PC1C 0 PC0C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output Port C function register 7 PCFC (0033H) bit Symbol Read/Write System Reset State Hot Reset State Function 0 - 6 PC6F 5 PC5F 4 PC4F W 3 PC3F 2 PC2F 1 PC1F 0 PC0F PC7F 0 - 0 - 0 - 0 - 0 - 0 - 0 - Refer to following table Port C drive register 7 PCDR (008CH) bit Symbol Read/Write System Reset State Hot Reset State Function PC2 setting 6 PC6D 5 PC5D 4 PC4D R/W 3 PC3D 2 PC2D 1 PC1D 0 PC0D PC7D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode PC1 setting PC0 setting Input port INT2 Output port Don't setting Input port INT1 Output port TA0IN input Input port INT0 Output port Don't setting PC5 setting PC4 setting PC3 setting Input port EA27 output Output port Reserved Input port EA26 output Output port Reserved Input port INT3 Output port TA2IN input PC7 setting PC6 setting Input port Don't setting Output port KO8output (Open-drain) Input port EA28 output Output port Reserved Note 1: A read-modify-write operation cannot be performed for the registers PCCR, PCFC. Note 2: When setting PC3-PC0 pins to INT3-INT0 input, set PCDR Figure 3.7.24 Register for Port C 92CF26A-138 2007-11-21 TMP92CF26A 3.7.10 Port F (PF0 to PF5, PF7) Ports F0 to F5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF5 to be input ports. It also sets all bits of the output latch register to "1". In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function as the output for I2S0, I2S1. A pin can be enabled for I/O by writing a "1" to the corresponding bit of the Port F Function Register (PFFC). Port F7 is a 1-bit general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Resetting sets PF7 to be an SDCLK output port. (1) Port F0 (I2S0CKO), Port F1 (I2S0DO), Port F2 (I2S0WS), Port F3 (I2S1CKO), Port F4 (I2S1DO), Port F5 (I2S1WS) Ports F0 to F5 are general-purpose I/O port. They also function as either I2S. Each pin is detailed below. I2Smode (I2S0Module) PF0 I2S0CKO (Clock output) I2S0DO (Data output) I2S0WS (Word-select output) PF4 I2Smode (I2S1Module) I2S1CKO (Clock output) I2S1DO (Data output) I2S1WS (Word-select output) PF1 PF2 PF5 PF6 92CF26A-139 2007-11-21 TMP92CF26A Reset Direction control (on bit basis) PFCR write Internal data bus Function control (on bit basis) PFFC write S Output latch PF write I2S0CKO output I2S1CKO output PF read A S PF0 (I2S0CKO) PF3 (I2S1CKO) Selector B SB Selector A Figure 3.7.25 Port F0, F3 Reset Direction control (on bit basis) PFCRwrite Function control (on bit basis) Internal data bus PFFC write S Output latch PF write I2S0DO,I2S1DO output I2S0WS,I2S1WS output A S PF1(I2S0DO) PF2(I2S0WS) PF4(I2S1DO) PF5(I2S1WS) Selector B SB Selector PF read A Figure 3.7.26 Port F1, F2, F4, F5 92CF26A-140 2007-11-21 TMP92CF26A (2) Port F7 (SDCLK), Port F7 is general-purpose output port. In addition to functioning as general-purpose output port, PF7 can also function as the SDCLK output. Reset Internal data bus Function control (on bit basis) PFFC write S Output latch SDCLK PF write AS Selector B PF7(SDCLK) PF read Figure 3.7.27 Port F7 92CF26A-141 2007-11-21 TMP92CF26A Port F register 7 PF (003CH) bit Symbol Read/Write System Reset State Hot Reset State PF7 R/W 1 - 6 5 PF5 4 PF4 3 PF3 R/W 2 PF2 1 PF1 0 PF0 Data from external port (Output latch register is set to "1") - Port F control register 7 PFCR (003EH) bit Symbol Read/Write System Reset State Hot Reset State Function 0 - 0 - 0 - 6 5 PF5C 4 PF4C 3 PF3C W 2 PF2C 1 PF1C 0 PF0C 0 - 0 - 0 - Refer to following table Port F function register 7 PFFC (003FH) bit Symbol Read/Write System Reset State Hot Reset State Function PF7F W 1 - 0: Port 1: SDCLK 6 5 PF5F 4 PF4F 3 PF3F W 2 PF2F 1 PF1F 0 PF0F 0 - 0 - 0 - 0 - 0 - 0 - Refer to following table Port F drive register 7 PFDR (008FH) bit Symbol Read/Write System Reset State Hot Reset State Function PF2 setting 6 PF6D 5 PF5D 4 PF4D R/W 3 PF3D 2 PF2D 1 PF1D 0 PF0D PF7D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode PF1 setting PF0 setting Input port Output port I2S0WS output Input port Output port I2S0DO output Input port Output port I2S0CKOoutput PF5 setting PF4 setting PF3 setting Input port Output port I2S1WS output Input port Output port I2S1DO output Input port Output port I2S1CKOoutput Note : A read-modify-write operation cannot be performed for the registers PFCR, PFFC and PFFC2. Figure 3.7.28 Register for Port F 92CF26A-142 2007-11-21 TMP92CF26A 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter. PG2 and PG3 can also be used as the MX and MY pins for a Touch screen interface. (PG) register is prohibited to access by byte. All the instruction (Arithmetic/Logical/ Bit operation and rotate/shift instruction) access by byte are prohibited. Word access is always needed. Internal data bus Port G read PG0(AN0), PG1(AN1), PG2(AN2,MX), PG3(AN3,MY, ADTRG ) PG4(AN4) PG5(AN5) Conversion Result Register AD Converter Channel Selector AD read ADTRG (for PG3 only) (PG2,PG3 only) TSICR0 Switch for TSI Typ.10 TSICR0 Figure 3.7.29 Port G 92CF26A-143 2007-11-21 TMP92CF26A Port G register 7 PG (0040H) Bit Symbol Read/Write System Reset State Hot Reset State 6 5 PG5 4 PG4 3 PG3 R 2 PG2 1 PG1 0 PG0 Data from external port - Note: The input channel selection of the AD converter and the permission of for ADTRG input are set by AD converter mode register ADMOD1. Port G Function register 7 PGFC (0043H) Bit Symbol Read/Write System Reset State Hot Reset State Function 6 5 4 3 PG3F W 0 - 0: Input port or AN3 1: ADTRG 2 1 0 Port G driver register 7 PGDR (0090H) Bit Symbol Read/Write System Reset State Hot Reset State Function 6 5 4 3 PG3D R/W 1 - 2 PG2D 1 0 1 - Input/Output buffer drive register for standby mode Note 1: A read-modify-write operation cannot be performed for the registers PGFC. Note 2: PG register is prohibited to access by byte. All the instruction (Arithmetic/ Logical/ Bit operation and rotate/ shift instruction) access by byte are prohibited. Word access is always needed. Example: LD wa, (PG) : Using only "a" register data, and cancel "w" register data. Note 3: Don't use PG register at the state that mingles Analog input and Digital input. Figure 3.7.30 Register for Port G 92CF26A-144 2007-11-21 TMP92CF26A 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to "1", and they output "1". PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as a port, Port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, and SDCKE), SRAM ( SRWR , SRLLB and SRLUB ) and NAND-Flash(NDALE and NDCLE). The above settings are made using the function register PJFC. However, either SDRAM or SRAM output signal for PJ0 to PJ2 are selected automatically according to the setting of the memory controller. Reset Function control2 (on bit basis) PJFC2 write Function control (on bit basis) PJFC write Selector Selector Internal data bus S PJ0( SDRAS , SRLLB ) PJ1 ( SDCAS , SRLUB ) PJ2( SDWE , SRWR ) PJ3(SDLLDQM) PJ4(SDLUDQM) PJ7(SDCKE) PJ write SRLLB , SRLUB , SRWR PJ read SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE Figure 3.7.31 Port J0 to J4 and J7 92CF26A-145 2007-11-21 TMP92CF26A Reset Direction control PJCR write Function control Internal data bus PJFC write S Output latch PJ write NDALE, NDCLE output A S PJ5 (NDALE), PJ6 (NDCLE) Selector B SB Selector PJ read A Figure 3.7.32 Port J5,J6 92CF26A-146 2007-11-21 TMP92CF26A Port J register 7 PJ bit Symbol PJ7 (004CH) Read/Write System Reset State 6 PJ6 5 PJ5 4 PJ4 R/W 3 PJ3 2 PJ2 1 PJ1 0 PJ0 Data from external port 1 - (Output latch register is set to "1") - 1 - 1 - 1 - 1 - 1 - Hot Reset State Port J control register 7 PJCR (004EH) bit Symbol Read/Write System Reset State Hot Reset State Function 6 PJ6C W 0 - 5 PJ5C 4 3 2 1 0 0 - 0: Input, 1: Output Port J function register 7 PJFC (004FH) bit Symbol Read/Write System Reset State Hot Reset State Function PJ7F 6 PJ6F 5 PJ5F 4 PJ4F W 3 PJ3F 2 PJ2F 1 PJ1F 0 PJ0F 0 - 0 - 0 - 0 - 0: Port 1:SDLUDQM 0 - 0: Port 1:SDLLDQM 0 - 0 - 0 - 0: Port 1: SDCKE 0: Port 1: NDCLE 0: Port 1: NDALE 0: Port 1: SDWE , SRWR 0: Port 0: Port 1: SDCAS , 1: SDRAS , SRLUB SRLLB Port J drive register 7 PJDR (0093H) bit Symbol Read/Write System Reset State Hot Reset State Function PJ7D 6 PJ6D 5 PJ5D 4 PJ4D R/W 3 PJ3D 2 PJ2D 1 PJ1D 0 PJ0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note: A read-modify-write operation cannot be performed for the registers PJCR and PJFC. Figure 3.7.33 Register for Port J 92CF26A-147 2007-11-21 TMP92CF26A 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to "0", and PK0 to PK7 pins output "0". In addition to functioning as an output port function, port K also functions as output pins for an LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and LGOE0 to LGOE2). The above settings are made using the function register PKFC. Reset Function control (on bit basis) PKFC write S Output latch Selector A B Output buffer PK write LCP0, LLOAD, LFR, LVSYNC, LHSYNC,LGOE0 to LGOE2 PK read PK0 (LCP0) PK1 (LLOAD) PK2 (LFR) PK3 (LVSYNC) PK4 (LHSYNC) PK5 (LGOE0) PK6 (LGOE1) PK7 (LGOE2) Internal data bus Figure 3.7.34 Port K0 to K7 92CF26A-148 2007-11-21 TMP92CF26A Port K register 7 PK (0050H) bit Symbol Read/Write System Reset State Hot Reset State PK7 6 PK6 5 PK5 4 PK4 R/W 3 PK3 2 PK2 1 PK1 0 PK0 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Port K function register 7 PKFC (0053H) bit Symbol Read/Write System Reset State Hot Reset State Function PK7F 6 PK6F 5 PK5F 4 PK4F W 3 PK3F 2 PK2F 1 PK1F 0 PK0F 0 - 0 - 0 - 0 - 0:Port 1: LHSYNC 0 - 0: Port 1: LVSYNC 0 - 0 - 0 - 0:Port 1:LGOE2 0:Port 1:LGOE1 0:Port 1:LGOE0 0: Port 1: LFR 0: Port 1: LLOAD 0: Port 1: LCP0 Port K drive register 7 PKDR (0094H) bit Symbol Read/Write System Reset State Hot Reset State Function PK7D 6 PK6D 5 PK5D 4 PK4D R/W 3 PK3D 2 PK2D 1 PK1D 0 PK0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note: A read-modify-write operation cannot be performed for the registers PKFC. Figure 3.7.35 Register for Port K 92CF26A-149 2007-11-21 TMP92CF26A 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to "0", and PL0 to PL7 pins output "0". In addition to functioning as a general-purpose output port, port L can also function as a data bus for an LCD controller (LD0 to LD7). The above settings are made using the function register PLFC. Reset Function control Internal data bus PLFC write R Output latch PL write LD0 to LD7 PL read A S PL0 to PL7 (LD0 to LD7) Selector B Figure 3.7.36 Port L0 to L7 92CF26A-150 2007-11-21 TMP92CF26A Port L register 7 PL bit Symbol PL7 (0054H) Read/Write System Reset State Hot Reset State 6 PL6 5 PL5 4 PL4 R/W 3 PL3 2 PL2 1 PL1 0 PL0 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Port L function register 7 PLFC bit Symbol PL7F (0057H) Read/Write System Reset State Hot Reset State Function 6 PL6F 5 PL5F 4 PL4F W 3 PL3F 2 PL2F 1 PL1F 0 PL0F 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Port 1: Data bus for LCDC (LD7 toLD0) Port L drive register 7 PLDR bit Symbol PL7D (0095H) Read/Write System Reset State Hot Reset State Function 6 PL6D 5 PL5D 4 PL4D R/W 3 PL3D 2 PL2D 1 PL1D 0 PL0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note: A read-modify-write operation cannot be performed for the registers PLFC. Figure 3.7.37 Register for Port L 92CF26A-151 2007-11-21 TMP92CF26A 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to "1", and PM1, PM2 and PM7 pins output "1". In addition to functioning as an output ports, port M also functions as output pin for the timers (TA1OUT), output pins for the RTC alarm ( ALARM ), and as the output pin for the melody/alarm generator (MLDALM, MLDALM ) and as the Power control pin (PWE). The above settings are made using the function register PMFC. PM1 has two output function which MLDALM and TA1OUT, and PM2 has two output functions ALARM and MLDALM . These are selected using PM Reset Function control PMFC write Internal data bus S Output latch S A Selector B PM write PM read TA1OUT MLDALM A S PM1 (MLDALM, TA1OUT) Selector B Figure 3.7.38 Port M1 92CF26A-152 2007-11-21 TMP92CF26A Reset Function control (on bit basis) PMFC write Internal data bus S Output latch S A Selector B PM write PM read MLDALM ALARM PM2 ( ALARM , MLDALM ) A S Selector B Figure 3.7.39 Port M2 Reset Function control (on bit basis) PMFC write S Output latch S A Selector B Internal data bus PM7 (PWE) PM write PM read PWE Figure 3.7.40 Port M7 92CF26A-153 2007-11-21 TMP92CF26A Port M register 7 PM (0058H) bit Symbol Read/Write System Reset State Hot Reset State PM7 R/W 1 - 6 5 4 3 2 PM2 R/W 1 - 1 PM1 0 1 - Port M function register 7 PMFC (005BH) bit Symbol Read/Write System Reset State Hot Reset State Function PM7F W 0 - 6 5 4 3 2 PM2F W 0 - 0: Port 1: ALARM at MLDALM 1 PM1F 0 0 - 0: Port 1: MLDALM at 0: Port 1: PWE at Port M drive register 7 PMDR (0096H) bit Symbol Read/Write System Reset State Hot Reset State Function PM7D R/W 1 - 6 5 4 3 2 PM2D R/W 1 - 1 PM1D 0 1 - Input /Output buffer drive register for standby mode Input/Output buffer drive register for standby mode Note: A read-modify-write operation cannot be performed for the registers PMFC. Figure 3.7.41 Register for Port M 92CF26A-154 2007-11-21 TMP92CF26A 3.7.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port N to an input port. In addition to functioning as a general-purpose I/O port, Port N can also function as key-board interface pin (KO0 to KO7) which can be set to open-drain output buffer. Reset Direction control (on bit basis) PNCR write Function control (on bit basis) PNFC write S Output latch PN write SB Selector PC read A PN0(KO0) to PN7(KO7) Open-drain enable Internal data bus Figure 3.7.42 Port N 92CF26A-155 2007-11-21 TMP92CF26A Port N register 7 PN (005CH) bit Symbol Read/Write System Reset State Hot Reset State PN7 6 PN6 5 PN5 4 PN4 R/W 3 PN3 2 PN2 1 PN1 0 PN0 Data from external port (Output latch register is set to "1") - Port N control register 7 PNCR (005EH) bit Symbol Read/Write System Reset State Hot Reset State Function PN7C 6 PN6C 5 PN5C 4 PN4C W 3 PN3C 2 PN2C 1 PN1C 0 PN0C 0 - 0 - 0 - 0 - 0: Input 0 - 1: Output 0 - 0 - 0 - Port N function register 7 PNFC (005FH) bit Symbol Read/Write System Reset State Hot Reset State Function PN7F 6 PN6F 5 PN5F 4 PN4F W 3 PN3F 2 PN2F 1 PN1F 0 PN0F 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: CMOS output 1: Open-drain output Port N drive register 7 PNDR (0097H) bit Symbol Read/Write System Reset State Hot Reset State Function PN7D 6 PN6D 5 PN5D 4 PN4D R/W 3 PN3D 2 PN2D 1 PN1D 0 PN0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note : A read-modify-write operation cannot be performed for the registers PNCR and PNFC. Figure 3.7.43 Register for Port N 92CF26A-156 2007-11-21 TMP92CF26A 3.7.17 Port P (PP1 to PP7) Ports P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port P1 to P5 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, P0 to P5 can also function as an output pin for timers (TA3OUT, TA5OUT, TA7OUT), as an input pin for timers (TB0IN0, TB1IN0), and as an input pin for external interruption (INT5 to INT7). Port P6 and P7 are 2-bit output port. Resetting sets output latch to "0". In addition to functioning as an output port, PP6 and PP7 can also function as an output pin for timers (TB0OUT0, TB1OUT1). Setting in the corresponding bits of PPCR and PPFC enables the respective functions. The edge select for external interruption is determined by the IIMC register in the interruption controller. In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and INT7 don't depend on IIMC1 register setting. INT6 and INT7 operate by setting TBnMOD Reset Direction control (on bit basis) PPCR write Internal data bus Function control (on bit basis) PPFC write R Output latch PP write TA3OUT output TA5OUT output A S PP1 (TA3OUT) PP2 (TA5OUT) Selector B SB Selector PP read A Figure 3.7.44 Port P1, P2 92CF26A-157 2007-11-21 TMP92CF26A Reset Direction control (on bit basis) PPCR write Function control (on bit basis) PPFC write R Output latch PP write TA7OUT SB Selector PP read A Level/edge selection and Rising/Falling selection IIMC Internal data bus Selector B INT5 Figure 3.7.45 Port P3 Reset Direction control (on bit basis) PPCR write Internal data bus Function control (on bit basis) PPFC write R Output latch PP4 (INT6,TB0IN0) PP5 (INT7, TB1IN0) PP write S B Selector PP read INT6 INT7 (from TMRB0) INT6 (from TMRB1) INT7 TB0IN0 TB1IN0 A Level/edge selection and Rising/Falling selection IIMC Figure 3.7.46 Port P4,P5 92CF26A-158 2007-11-21 TMP92CF26A Reset Function control (on bit basis) PPFC write R Output latch PP write TB0OUT0 output TB1OUT0 output A S PP6 (TB0OUT0) PP7 (TB1OUT0) Internal data bus Selector B Figure 3.7.47 Port P6, P7 92CF26A-159 2007-11-21 TMP92CF26A Port P register 7 PP (0060H) bit Symbol Read/Write System Reset State Hot Reset State PP7 6 PP6 5 PP5 4 PP4 R/W 3 PP3 2 PP2 1 PP1 0 0 - 0 - Data from external port (Output latch register is cleared to "0") - Port P control register 7 PPCR (0062H) bit Symbol Read/Write System Reset State Hot Reset State Function 6 5 PP5C 4 PP4C 3 PP3C W 2 PP2C 1 PP1C 0 0 - 0 - 0 - 0: Input 1: Output 0 - 0 - Port P function register 7 PPFC (0063H) bit Symbol Read/Write System Reset State Hot Reset State Function PP7F 6 PP6F 5 PP5F 4 PP4F W 3 PP3F 2 PP2F 1 PP1F 0 0 - 0:Port 1:TB1OUT0 0 - 0:Port 1:TB0OUT0 0 - 0 - 0 - Refer to following table 0 - 0 - Port P drive register 7 PPDR (0098H) bit Symbol Read/Write System Reset State Hot Reset State Function PP3 setting 6 PP6D 5 PP5D 4 PP4D R/W 3 PP3D 2 PP2D 1 PP1D 0 PP7D 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode PP2 setting PP1 setting 0 1 Input port INT5 input Output port TA7OUT output PP5 setting PP4 setting Note1: A read-modify-write operation cannot be performed for the registers PPCR, PPFC. Note2: When setting PP5, PP4, PP3 pins to INT7,INT6,INT5 input, set PPDR Figure 3.7.48 Register for Port P 92CF26A-160 2007-11-21 TMP92CF26A 3.7.18 Port R (R0 to R3) Ports R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port R0 to R3 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, PR0 to PR3 can also function as the SPI controller pin (SPCLK, SPCS , SPDO and SPDI). Setting in the corresponding bits of PFCR and PFFC enables the respective functions. Reset SPICT Direction control (on bit basis) PRCR write Function control (on bit basis) PRFC write R Output latch PR write SB Selector PR read SPDI input A PR0(SPDI) Internal data bus Figure 3.7.49 Port R0 92CF26A-161 2007-11-21 TMP92CF26A Reset SPICT Direction control (on bit basis) PRCR write Function control (on bit basis) PRFC write R Output latch PR write SPDO, SPCS , SPCLK PR read S A Selector B SB Selector A PR1(SPDO), PR2( SPCS ), PR3(SPCLK) Internal data bus Figure 3.7.50 Port R1 to R3 92CF26A-162 2007-11-21 TMP92CF26A Port R register 7 PR (0064H) bit Symbol Read/Write System Reset State Hot Reset State 6 5 4 3 PR3 2 PR2 R/W 1 PR1 0 PR0 Data from external port (Output latch register is cleared to "0") - Port R control register 7 PRCR (0066H) bit Symbol Read/Write System Reset State Hot Reset State Function 6 5 4 3 PR3C 2 PR2C W 1 PR1C 0 PR0C 0 - 0 - 0 - 0 - 0: Input, 1: Output Port R function register 7 PRFC (0067H) bit Symbol Read/Write System Reset State Hot Reset State Function 6 5 4 3 PR3F 2 PR2F W 1 PR1F 0 PR0F 0 - 0: Port 1: SPCLK 0 - 0: Port 1: SPCS 0 - 0: Port 1: SPDO 0 - 0: Port 1: SPDI Port R drive register 7 PRDR bit Symbol (0099H) Read/Write System Reset State Hot Reset State Function 6 5 4 3 PR3D 2 PR2D R/W 1 PR1D 0 PR0D 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode PR1 setting PR0 setting Input port Reserved Output port SPDO output Input port SPDI input Output port Reserved PR3setting PR2 setting Input port Reserved Output port SPCLK output Input port Reserved Output port SPCS Output Note: A read-modify-write operation cannot be performed for the registers PRCR, PRFC. Figure 3.7.51 Register for Port R 92CF26A-163 2007-11-21 TMP92CF26A 3.7.19 Port T (PT0 to PT7) Ports T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports T0 to T7 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, PT0 to PT7 can also function as a data bus pin for LCD controller (LD8 to LD15). Setting in the corresponding bits of PTCR and PTFC enables the respective functions. Reset Direction control (on bit basis) PTCR write Function control (on bit basis) PTFC write S Output latch PT write LD8 to LD15 Internal data bus A S PT0 to PT7 (LD8 to LD15) Selector B SB Selector PT read A Figure 3.7.52 Port T0 to T7 92CF26A-164 2007-11-21 TMP92CF26A Port T register 7 PT bit Symbol PT7 (00A0H) Read/Write System Reset State Hot Reset State 6 PT6 5 PT5 4 PT4 R/W 3 PT3 2 PT2 1 PT1 0 PT0 Data from external port (Output latch register is cleared to "0") - Port T control register 7 PTCR bit Symbol PT7C (00A2H) Read/Write System Reset State Hot Reset State Function 6 PT6C 5 PT5C 4 PT4C W 3 PT3C 2 PT2C 1 PT1C 0 PT0C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output Port T function register 7 PTFC bit Symbol PT7F (00A3H) Read/Write System Reset State Hot Reset State Function 6 PT6F 5 PT5F 4 PT4F W 3 PT3F 2 PT2F 1 PT1F 0 PT0F 0 - 0 - 0 - 0: Port 0 - 0 - 0 - 0 - 0 - 1: Data bus for LCDC (LD15 to LD8) Port T drive register 7 PTDR bit Symbol PT7D (009BH) Read/Write System Reset State Hot Reset State Function 6 PT6D 5 PT5D 4 PT4D R/W 3 PT3D 2 PT2D 1 PT1D 0 PT0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for the registers PTCR, PTFC. Note2: When PT is used as LD15 to LD8, set applicable PTnC to"1". Figure 3.7.53 Register for Port T 92CF26A-165 2007-11-21 TMP92CF26A 3.7.20 Port U (PU0 to PU7) Ports U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port U0 to U7 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, PU0 to PU7 can also function as a data bus pin for LCD controller (LD16 to LD23) and as the SDCLK input function. Setting in the corresponding bits of PUCR and PUFC enables the respective functions. In addition to functioning as above function, PU7 can also function as the communication for debug mode (EO_TRGOUT). These functions are operated when it is started in debug mode. In this case, PU7 can not be used as LD23 function. Reset Direction control (on bit basis) PUCR write Function control (on bit basis) PUFC write R Output latch PU write LD16 to LD20, LD22,LD23 EO_TRGOUT Debug mode Internal data bus A S PU0~PU4,PU6 (LD16 to LD20,LD22) PU7 (LD23,EO_TRGOUT) Selector B C SB Selector PU read A Figure 3.7.54 Port U0 to U4 , U6 , U7 92CF26A-166 2007-11-21 TMP92CF26A Reset Direction control (on bit basis) PUCR wirte Function control (on bit basis) Internal data bus PUFC write R Output latch PU write LD21 SB Selector PU read A AS Selector B PU5 (LD21) Figure 3.7.55 Port U5 92CF26A-167 2007-11-21 TMP92CF26A Port U register 7 PU (00A4H) Bit Symbol Read/Write System Reset State Hot Reset State PU7 6 PU6 5 PU5 4 PU4 R/W 3 PU3 2 PU2 1 PU1 0 PU0 Data from external port (Output latch register is cleared to "0") - Port U control register 7 PUCR (00A6H) Bit Symbol Read/Write System Reset State Hot Reset State Function PU7C 6 PU6C 5 PU5C 4 PU4C W 3 PU3C 2 PU2C 1 PU1C 0 PU0C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output Port U function register 7 PUFC (00A7H) Bit Symbol Read/Write System Reset State Hot Reset State Function PU7F 6 PU6F 5 PU5F 4 PU4F W 3 PU3F 2 PU2F 1 PU1F 0 PU0F 0 - 0: Port 1: LD23 0 - 0: Port 1: LD22 0 - 0: Port 1: LD21@ 0 - 0: Port 1: LD20 0 - 0: Port 1: LD19 0 - 0: Port 1: LD18 0 - 0: Port 1: LD17 0 - 0: Port 1: LD16 Note: When PU is used as LD23 to LD16, set applicable PUnC to "1". Port U drive register 7 PUDR (009CH) Bit Symbol Read/Write System Reset State Hot Reset State Function PU7D 6 PU6D 5 PU5D 4 PU4D R/W 3 PU3D 2 PU2D 1 PU1D 0 PU0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note1: A read-modify-write operation cannot be performed for the registers PUCR, PUFC. Note2: When use PU as LD23 to LD16, set PUnC to "1". When use PU5 as LD21, set PU5C to "1". Figure 3.7.56 Register for Port U 92CF26A-168 2007-11-21 TMP92CF26A 3.7.21 Port V (PV0 to PV4, PV6, PV7) Ports V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, PV can also function as a input or output pin for SBI (SDA, SCL) and an output for SIO(SCLK0) (Note). Setting in the corresponding bits of PVCR and PVFC enables the respective functions. Ports V3 and V4 are 2-bit general-purpose output ports. Resetting clear ports V3 and V4 to output latch to "0". Reset Direction control (on bit basis) PVCR write Internal data bus Function control (on bit basis) PVFC write R Output latch A S Selector PV write SCLK0 output SB Selector A PV read B PV0 (SCLK0) PV1 PV2 Note: SIO function support function that input clock from SCLK0, basically. However, if setting to PV0 pin, this function supports only the output function. Figure 3.7.57 Port V0 to V2 92CF26A-169 2007-11-21 TMP92CF26A Reset Internal data bus R Output latch PV3 PV4 PV write PV read Figure 3.7.58 Port V3, V4 Reset Direction control (on bit basis) PVCR write Function control (on bit basis) PVFC write R Output latch PV write SDA,SCL output A S PV6(SDA) Open-drain enable PVFC2 Internal data bus Selector B PV7(SCL) SB Selector PV read SDA,SCL input A Figure 3.7.59 Port V6, V7 92CF26A-170 2007-11-21 TMP92CF26A Port V register 4 PV4 7 PV bit Symbol PV7 (00A8H) Read/Write System Reset State Hot Reset State 6 PV6 5 3 PV3 2 PV2 R/W 1 PV1 0 PV0 R/W Data from external port (Output latch register is cleared to "0") - Data from external port (Output latch register is cleared to "0") - 7 PVCR bit Symbol PV7C (00AAH) Read/Write System Reset State Hot Reset State Function 6 PV6C Port V control register 5 4 3 2 PV2C 1 PV1C W 0 PV0C 0 - 0 - 0 - 0 - 0: Input 1: Output 0 - 0: Input 1: Output 7 PVFC (00ABH) bit Symbol Read/Write System Reset State Hot Reset State Function PV7F W 0 - 6 PV6F Port V function register 5 4 3 2 PV2F 1 PV1F W 0 PV0F 0 - 0 - 0 - Refer to following table 0 - Refer to following table 7 PVFC2 (00A9H) bit Symbol Read/Write System Reset State Hot Reset State Function PV7F2 W 0 - 0: CMOS 1: Open -drain 6 PV6F2 Port V function register 2 5 4 3 2 1 0 0 - 0: CMOS 1: Open -drain 7 PVDR bit Symbol PV7D R/W 1 - (009DH) Read/Write System Reset State Hot Reset State Function PV2 setting 6 PV6D Port V drive register 5 4 3 PV4D PV3D 2 PV2D R/W 1 PV1D 0 PV0D 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode PV1 setting PV0 setting 0 Input port Reserved 1 Output port Reserved 0 Input port Reserved 1 Output port Reserved 0 Input port Reserved 1 Output port SCLK0 output 0 1 PV7 setting 0 1 PV6 setting 0 1 Note: SCLK0 is only output. 0 Input port Reserved 1 Output port SDA I/O 0 Input port Reserved 1 Output port SCL I/O 0 1 0 1 Note: A read-modify-write operation cannot be performed for the registers PVCR, PVFC and PVFC2. Figure 3.7.60 Register for Port V 92CF26A-171 2007-11-21 TMP92CF26A 3.7.22 Port W (PW0 to PW7) Ports W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports W0 to W7 to input port and output latch to "0". Setting in the corresponding bits of PWCR and PWFC enables the respective functions. Reset Direction control (on bit basis) PWCR write Function control (on bit basis) PWFC write R Output latch PW write SB Selector PW read A PW0 to PW7 Internal data bus Figure 3.7.61 Port W0 to W7 92CF26A-172 2007-11-21 TMP92CF26A Port W register 7 PW (00ACH) bit Symbol Read/Write System Reset State Hot Reset State PW7 6 PW6 5 PW5 4 PW4 R/W 3 PW3 2 PW2 1 PW1 0 PW0 Data from external port (Output latch register is cleared to "0") - Port W control register 7 PWCR (00AEH) bit Symbol Read/Write System Reset State Hot Reset State Function PW7C 6 PW6C 5 PW5C 4 PW4C W 3 PW3C 2 PW2C 1 PW1C 0 PW0C 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0: Input 1: Output Port W function register 7 PWFC (00AFH) bit Symbol Read/Write System Reset State Hot Reset State Function PW7F 6 PW6F 5 PW5F 4 PW4F W 3 PW3F 2 PW2F 1 PW1F 0 PW0F 0 - 0 - 0 - 0 - 0: Port 0 - 1: Reserved 0 - 0 - 0 - Port W drive register 7 PWDR (009EH) bit Symbol Read/Write System Reset State Hot Reset State Function PW7D 6 PW6D 5 PW5D 4 PW4D R/W 3 PW3D 2 PW2D 1 PW1D 0 PW0D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - Input/Output buffer drive register for standby mode Note2: A read-modify-write operation cannot be performed for the registers PWCR, PWFC. Figure 3.7.62 Register for Port W 92CF26A-173 2007-11-21 TMP92CF26A 3.7.23 Port X (PX4, PX5 and PX7) Ports X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports X5 and X7 to input port and output latch to "0". In addition to functioning as general-purpose I/O port, PX5 and PX7 can also function as the USB clock input pin (X1USB). Setting in the corresponding bits of PXCR and PXFC enables the respective functions. Port X4 is 1-bit general-purpose output port. Resetting sets output latch to "0". In addition to functioning as general-purpose output port, PX4 can also function as a system clock output pin (CLKOUT) and as an output pin (LDIV). Setting in the corresponding bits of PX and PXFC enables the respective functions. Reset Function control (on bit basis) PXFC write R Output latch A PX write Internal data bus S PX4 (CLKOUT) (LDIV) Selector B PX read CLKOUT output A S Selector LDIV output B Figure 3.7.63 Port X4 92CF26A-174 2007-11-21 TMP92CF26A Reset Direction control (on bit basis) PXCR write Function control (on bit basis) PXFC write R Output latch PX write SB Selector PX read X1USB input A PX5 (X1USB) PX7 Internal data bus Figure 3.7.64 Port X5, X7 92CF26A-175 2007-11-21 TMP92CF26A Port X register 7 PX bit Symbol System Reset State Hot Reset State PX7 R/W (00B0H) Read/Write 6 5 PX5 R/W 4 PX4 Note2) 3 2 1 0 Data from external port (Output latch register is cleared to "0") - Port X control register 7 PXCR bit Symbol PX7C W 0 - 0: Input 1: Output (00B2H) Read/Write System Reset State Hot Reset State Function 6 5 PX5C W 0 - 0: Input 1: Output 4 3 2 1 0 Port X function register 7 PXFC bit Symbol PX7F W 0 - 0:Port 1:Reserved 6 5 PX5F W 0 - 0:Port 1:X1USB input 4 PX4F 3 2 1 0 (00B3H) Read/Write System Reset State Hot Reset State Function 0 - Refer to following table Port X drive register 7 PXDR bit Symbol PXD7 R/W 1 - 1 - Input/Output buffer drive register for standby mode Note 1: A read-modify-write operation cannot be performed for the registers PXCR, PXFC. Note 2: When PXFC |